| commit | 7b50965161cd36f3175ae161d370cb6ed6cac0ae | [log] [tgz] |
|---|---|---|
| author | Vijayavardhan Vennapusa <vvreddy@codeaurora.org> | Fri Jul 28 11:23:47 2017 +0530 |
| committer | Vijayavardhan Vennapusa <vvreddy@codeaurora.org> | Fri Sep 14 13:08:02 2018 +0530 |
| tree | e53e5fbe602478b5ec9698b164363428e48635fc | |
| parent | 64516c4613a755bea650ff02590ab8c18606ef08 [diff] |
dwc3-msm: Add delay between consecutive register reads in while loop Add some delay between two consecutive register reads in while loop so that to avoid traffic congestion on NOCs. Change-Id: I6efb8c91e0d07160ccce593a23898b2259cb1ebf Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>