| commit | 7c1c7c18fc752b2a1d07597286467ef186312463 | [log] [tgz] |
|---|---|---|
| author | Alex Deucher <alexander.deucher@amd.com> | Fri Apr 05 10:28:08 2013 -0400 |
| committer | Alex Deucher <alexander.deucher@amd.com> | Tue Apr 09 10:23:50 2013 -0400 |
| tree | 9e66c767d5dd67f96109c7654f9d46ee33abdaf2 | |
| parent | 9ed8b1f93ca3a274079cb36826af1331f83cd118 [diff] [blame] |
drm/radeon/dce6: add missing display reg for tiling setup A new tiling config register for the display blocks was added on DCE6. May fix: https://bugs.freedesktop.org/show_bug.cgi?id=62889 https://bugs.freedesktop.org/show_bug.cgi?id=57919 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index 23fc08f..f84cff0 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h
@@ -65,6 +65,8 @@ #define DMIF_ADDR_CONFIG 0xBD4 +#define DMIF_ADDR_CALC 0xC00 + #define SRBM_STATUS 0xE50 #define GRBM_RQ_PENDING (1 << 5) #define VMC_BUSY (1 << 8)