tree 7956944a101488724bea59c15c7db7bcc2fa606a
parent 8bb495e3f02401ee6f76d1b1d77f3ac9f079e376
author Shawn Guo <shawn.guo@linaro.org> 1372666570 +0800
committer Mark Brown <broonie@linaro.org> 1372673540 +0100

ASoC: mxs: register saif mclk to clock framework

Mostly the mxs system design uses saif0 mclk output as the clock source
of codec.  Since the mclk is implemented as a general divider with the
saif clk as the parent clock, let's register the mclk as a basic
clk-divider to common clock framework.  Then with it being a clock
provdier, clk_get() call in codec driver probe function will just work.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>