tree 12de4a2d85e099eda0b466a95dc8fae7ea034296
parent 8cc3e169a606ab9577a333a2017cb1acf75668e3
author Daniel Vetter <daniel.vetter@ffwll.ch> 1403722907 +0300
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1405022677 +0200

drm/i915: Remove spll_refcount for hsw

SPLL would be a reference clock we could potentially share,
especially if we want to use the SSC mode. But currently we
don't, so let's rip out this complexity for a simpler conversion
to the new display pll framework.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>