staging: brcm80211: fix 'ERROR: "foo * bar" should be "foo *bar"'
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
diff --git a/drivers/staging/brcm80211/util/aiutils.c b/drivers/staging/brcm80211/util/aiutils.c
index 8883af0..0078884 100644
--- a/drivers/staging/brcm80211/util/aiutils.c
+++ b/drivers/staging/brcm80211/util/aiutils.c
@@ -31,7 +31,7 @@
/* EROM parsing */
static uint32
-get_erom_ent(si_t * sih, uint32 ** eromptr, uint32 mask, uint32 match)
+get_erom_ent(si_t *sih, uint32 **eromptr, uint32 mask, uint32 match)
{
uint32 ent;
uint inv = 0, nom = 0;
@@ -66,8 +66,8 @@
}
static uint32
-get_asd(si_t * sih, uint32 ** eromptr, uint sp, uint ad, uint st,
- uint32 * addrl, uint32 * addrh, uint32 * sizel, uint32 * sizeh)
+get_asd(si_t *sih, uint32 **eromptr, uint sp, uint ad, uint st,
+ uint32 *addrl, uint32 *addrh, uint32 *sizel, uint32 *sizeh)
{
uint32 asd, sz, szd;
@@ -100,12 +100,12 @@
return asd;
}
-static void ai_hwfixup(si_info_t * sii)
+static void ai_hwfixup(si_info_t *sii)
{
}
/* parse the enumeration rom to identify all cores */
-void BCMATTACHFN(ai_scan) (si_t * sih, void *regs, uint devid) {
+void BCMATTACHFN(ai_scan) (si_t *sih, void *regs, uint devid) {
si_info_t *sii = SI_INFO(sih);
chipcregs_t *cc = (chipcregs_t *) regs;
uint32 erombase, *eromptr, *eromlim;
@@ -310,7 +310,7 @@
/* This function changes the logical "focus" to the indicated core.
* Return the current core's virtual address.
*/
-void *ai_setcoreidx(si_t * sih, uint coreidx)
+void *ai_setcoreidx(si_t *sih, uint coreidx)
{
si_info_t *sii = SI_INFO(sih);
uint32 addr = sii->coresba[coreidx];
@@ -371,13 +371,13 @@
}
/* Return the number of address spaces in current core */
-int ai_numaddrspaces(si_t * sih)
+int ai_numaddrspaces(si_t *sih)
{
return 2;
}
/* Return the address of the nth address space in the current core */
-uint32 ai_addrspace(si_t * sih, uint asidx)
+uint32 ai_addrspace(si_t *sih, uint asidx)
{
si_info_t *sii;
uint cidx;
@@ -396,7 +396,7 @@
}
/* Return the size of the nth address space in the current core */
-uint32 ai_addrspacesize(si_t * sih, uint asidx)
+uint32 ai_addrspacesize(si_t *sih, uint asidx)
{
si_info_t *sii;
uint cidx;
@@ -414,7 +414,7 @@
}
}
-uint ai_flag(si_t * sih)
+uint ai_flag(si_t *sih)
{
si_info_t *sii;
aidmp_t *ai;
@@ -429,11 +429,11 @@
return (R_REG(sii->osh, &ai->oobselouta30) & 0x1f);
}
-void ai_setint(si_t * sih, int siflag)
+void ai_setint(si_t *sih, int siflag)
{
}
-void ai_write_wrap_reg(si_t * sih, uint32 offset, uint32 val)
+void ai_write_wrap_reg(si_t *sih, uint32 offset, uint32 val)
{
si_info_t *sii = SI_INFO(sih);
uint32 *w = (uint32 *) sii->curwrap;
@@ -441,7 +441,7 @@
return;
}
-uint ai_corevendor(si_t * sih)
+uint ai_corevendor(si_t *sih)
{
si_info_t *sii;
uint32 cia;
@@ -451,7 +451,7 @@
return ((cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT);
}
-uint ai_corerev(si_t * sih)
+uint ai_corerev(si_t *sih)
{
si_info_t *sii;
uint32 cib;
@@ -461,7 +461,7 @@
return ((cib & CIB_REV_MASK) >> CIB_REV_SHIFT);
}
-bool ai_iscoreup(si_t * sih)
+bool ai_iscoreup(si_t *sih)
{
si_info_t *sii;
aidmp_t *ai;
@@ -483,7 +483,7 @@
* Also, when using pci/pcie, we can optimize away the core switching for pci registers
* and (on newer pci cores) chipcommon registers.
*/
-uint ai_corereg(si_t * sih, uint coreidx, uint regoff, uint mask, uint val)
+uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
{
uint origidx = 0;
uint32 *r = NULL;
@@ -570,7 +570,7 @@
return (w);
}
-void ai_core_disable(si_t * sih, uint32 bits)
+void ai_core_disable(si_t *sih, uint32 bits)
{
si_info_t *sii;
volatile uint32 dummy;
@@ -598,7 +598,7 @@
* bits - core specific bits that are set during and after reset sequence
* resetbits - core specific bits that are set only during reset sequence
*/
-void ai_core_reset(si_t * sih, uint32 bits, uint32 resetbits)
+void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
{
si_info_t *sii;
aidmp_t *ai;
@@ -626,7 +626,7 @@
OSL_DELAY(1);
}
-void ai_core_cflags_wo(si_t * sih, uint32 mask, uint32 val)
+void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)
{
si_info_t *sii;
aidmp_t *ai;
@@ -651,7 +651,7 @@
}
}
-uint32 ai_core_cflags(si_t * sih, uint32 mask, uint32 val)
+uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val)
{
si_info_t *sii;
aidmp_t *ai;
@@ -677,7 +677,7 @@
return R_REG(sii->osh, &ai->ioctrl);
}
-uint32 ai_core_sflags(si_t * sih, uint32 mask, uint32 val)
+uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val)
{
si_info_t *sii;
aidmp_t *ai;
@@ -704,7 +704,7 @@
}
#ifdef BCMDBG
-void ai_view(si_t * sih, bool verbose)
+void ai_view(si_t *sih, bool verbose)
{
si_info_t *sii;
osl_t *osh;
diff --git a/drivers/staging/brcm80211/util/bcmotp.c b/drivers/staging/brcm80211/util/bcmotp.c
index c85cc6a..88e8720 100644
--- a/drivers/staging/brcm80211/util/bcmotp.c
+++ b/drivers/staging/brcm80211/util/bcmotp.c
@@ -55,11 +55,11 @@
/* OTP common function type */
typedef int (*otp_status_t) (void *oh);
typedef int (*otp_size_t) (void *oh);
-typedef void *(*otp_init_t) (si_t * sih);
-typedef uint16(*otp_read_bit_t) (void *oh, chipcregs_t * cc, uint off);
-typedef int (*otp_read_region_t) (si_t * sih, int region, uint16 * data,
- uint * wlen);
-typedef int (*otp_nvread_t) (void *oh, char *data, uint * len);
+typedef void *(*otp_init_t) (si_t *sih);
+typedef uint16(*otp_read_bit_t) (void *oh, chipcregs_t *cc, uint off);
+typedef int (*otp_read_region_t) (si_t *sih, int region, uint16 *data,
+ uint *wlen);
+typedef int (*otp_nvread_t) (void *oh, char *data, uint *len);
/* OTP function struct */
typedef struct otp_fn_s {
@@ -170,7 +170,7 @@
return (int)oi->wsize * 2;
}
-static uint16 ipxotp_otpr(void *oh, chipcregs_t * cc, uint wn)
+static uint16 ipxotp_otpr(void *oh, chipcregs_t *cc, uint wn)
{
otpinfo_t *oi;
@@ -182,7 +182,7 @@
return R_REG(oi->osh, &cc->sromotp[wn]);
}
-static uint16 ipxotp_read_bit(void *oh, chipcregs_t * cc, uint off)
+static uint16 ipxotp_read_bit(void *oh, chipcregs_t *cc, uint off)
{
otpinfo_t *oi = (otpinfo_t *) oh;
uint k, row, col;
@@ -214,7 +214,7 @@
/* Calculate max HW/SW region byte size by substracting fuse region and checksum size,
* osizew is oi->wsize (OTP size - GU size) in words
*/
-static int ipxotp_max_rgnsz(si_t * sih, int osizew)
+static int ipxotp_max_rgnsz(si_t *sih, int osizew)
{
int ret = 0;
@@ -233,7 +233,7 @@
return ret;
}
-static void BCMNMIATTACHFN(_ipxotp_init) (otpinfo_t * oi, chipcregs_t * cc) {
+static void BCMNMIATTACHFN(_ipxotp_init) (otpinfo_t *oi, chipcregs_t *cc) {
uint k;
uint32 otpp, st;
@@ -302,7 +302,7 @@
oi->flim = oi->wsize;
}
-static void *BCMNMIATTACHFN(ipxotp_init) (si_t * sih) {
+static void *BCMNMIATTACHFN(ipxotp_init) (si_t *sih) {
uint idx;
chipcregs_t *cc;
otpinfo_t *oi;
@@ -366,7 +366,7 @@
return (void *)oi;
}
-static int ipxotp_read_region(void *oh, int region, uint16 * data, uint * wlen)
+static int ipxotp_read_region(void *oh, int region, uint16 *data, uint *wlen)
{
otpinfo_t *oi = (otpinfo_t *) oh;
uint idx;
@@ -452,7 +452,7 @@
return 0;
}
-static int ipxotp_nvread(void *oh, char *data, uint * len)
+static int ipxotp_nvread(void *oh, char *data, uint *len)
{
return BCME_UNSUPPORTED;
}
@@ -560,7 +560,7 @@
return ((int)(oi->size));
}
-static uint16 hndotp_otpr(void *oh, chipcregs_t * cc, uint wn)
+static uint16 hndotp_otpr(void *oh, chipcregs_t *cc, uint wn)
{
otpinfo_t *oi = (otpinfo_t *) oh;
osl_t *osh;
@@ -575,7 +575,7 @@
return (R_REG(osh, &ptr[wn]));
}
-static uint16 hndotp_otproff(void *oh, chipcregs_t * cc, int woff)
+static uint16 hndotp_otproff(void *oh, chipcregs_t *cc, int woff)
{
otpinfo_t *oi = (otpinfo_t *) oh;
osl_t *osh;
@@ -592,7 +592,7 @@
return (R_REG(osh, &ptr[(oi->size / 2) + woff]));
}
-static uint16 hndotp_read_bit(void *oh, chipcregs_t * cc, uint idx)
+static uint16 hndotp_read_bit(void *oh, chipcregs_t *cc, uint idx)
{
otpinfo_t *oi = (otpinfo_t *) oh;
uint k, row, col;
@@ -623,7 +623,7 @@
return (uint16) st;
}
-static void *BCMNMIATTACHFN(hndotp_init) (si_t * sih) {
+static void *BCMNMIATTACHFN(hndotp_init) (si_t *sih) {
uint idx;
chipcregs_t *cc;
otpinfo_t *oi;
@@ -697,7 +697,7 @@
return ret;
}
-static int hndotp_read_region(void *oh, int region, uint16 * data, uint * wlen)
+static int hndotp_read_region(void *oh, int region, uint16 *data, uint *wlen)
{
otpinfo_t *oi = (otpinfo_t *) oh;
uint32 idx, st;
@@ -727,7 +727,7 @@
return 0;
}
-static int hndotp_nvread(void *oh, char *data, uint * len)
+static int hndotp_nvread(void *oh, char *data, uint *len)
{
int rc = 0;
otpinfo_t *oi = (otpinfo_t *) oh;
@@ -885,7 +885,7 @@
return readBit;
}
-void *BCMNMIATTACHFN(otp_init) (si_t * sih) {
+void *BCMNMIATTACHFN(otp_init) (si_t *sih) {
otpinfo_t *oi;
void *ret = NULL;
@@ -917,8 +917,8 @@
}
int
-BCMNMIATTACHFN(otp_read_region) (si_t * sih, int region, uint16 * data,
- uint * wlen) {
+BCMNMIATTACHFN(otp_read_region) (si_t *sih, int region, uint16 *data,
+ uint *wlen) {
bool wasup = FALSE;
void *oh;
int err = 0;
@@ -946,7 +946,7 @@
return err;
}
-int otp_nvread(void *oh, char *data, uint * len)
+int otp_nvread(void *oh, char *data, uint *len)
{
otpinfo_t *oi = (otpinfo_t *) oh;
diff --git a/drivers/staging/brcm80211/util/bcmsrom.c b/drivers/staging/brcm80211/util/bcmsrom.c
index d5527f75..31f6ad8 100644
--- a/drivers/staging/brcm80211/util/bcmsrom.c
+++ b/drivers/staging/brcm80211/util/bcmsrom.c
@@ -65,38 +65,38 @@
#define SROM_CIS_SINGLE 1
-static int initvars_srom_si(si_t * sih, osl_t * osh, void *curmap, char **vars,
- uint * count);
-static void _initvars_srom_pci(uint8 sromrev, uint16 * srom, uint off,
- varbuf_t * b);
-static int initvars_srom_pci(si_t * sih, void *curmap, char **vars,
- uint * count);
-static int initvars_flash_si(si_t * sih, char **vars, uint * count);
+static int initvars_srom_si(si_t *sih, osl_t *osh, void *curmap, char **vars,
+ uint *count);
+static void _initvars_srom_pci(uint8 sromrev, uint16 *srom, uint off,
+ varbuf_t *b);
+static int initvars_srom_pci(si_t *sih, void *curmap, char **vars,
+ uint *count);
+static int initvars_flash_si(si_t *sih, char **vars, uint *count);
#ifdef BCMSDIO
-static int initvars_cis_sdio(osl_t * osh, char **vars, uint * count);
-static int sprom_cmd_sdio(osl_t * osh, uint8 cmd);
-static int sprom_read_sdio(osl_t * osh, uint16 addr, uint16 * data);
+static int initvars_cis_sdio(osl_t *osh, char **vars, uint *count);
+static int sprom_cmd_sdio(osl_t *osh, uint8 cmd);
+static int sprom_read_sdio(osl_t *osh, uint16 addr, uint16 *data);
#endif /* BCMSDIO */
-static int sprom_read_pci(osl_t * osh, si_t * sih, uint16 * sprom, uint wordoff,
- uint16 * buf, uint nwords, bool check_crc);
+static int sprom_read_pci(osl_t *osh, si_t *sih, uint16 *sprom, uint wordoff,
+ uint16 *buf, uint nwords, bool check_crc);
#if defined(BCMNVRAMR)
-static int otp_read_pci(osl_t * osh, si_t * sih, uint16 * buf, uint bufsz);
+static int otp_read_pci(osl_t *osh, si_t *sih, uint16 *buf, uint bufsz);
#endif
-static uint16 srom_cc_cmd(si_t * sih, osl_t * osh, void *ccregs, uint32 cmd,
+static uint16 srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, uint32 cmd,
uint wordoff, uint16 data);
-static int initvars_table(osl_t * osh, char *start, char *end, char **vars,
- uint * count);
-static int initvars_flash(si_t * sih, osl_t * osh, char **vp, uint len);
+static int initvars_table(osl_t *osh, char *start, char *end, char **vars,
+ uint *count);
+static int initvars_flash(si_t *sih, osl_t *osh, char **vp, uint len);
/* Initialization of varbuf structure */
-static void BCMATTACHFN(varbuf_init) (varbuf_t * b, char *buf, uint size) {
+static void BCMATTACHFN(varbuf_init) (varbuf_t *b, char *buf, uint size) {
b->size = size;
b->base = b->buf = buf;
}
/* append a null terminated var=value string */
-static int BCMATTACHFN(varbuf_append) (varbuf_t * b, const char *fmt, ...) {
+static int BCMATTACHFN(varbuf_append) (varbuf_t *b, const char *fmt, ...) {
va_list ap;
int r;
size_t len;
@@ -151,8 +151,8 @@
* Return 0 on success, nonzero on error.
*/
int
-BCMATTACHFN(srom_var_init) (si_t * sih, uint bustype, void *curmap, osl_t * osh,
- char **vars, uint * count) {
+BCMATTACHFN(srom_var_init) (si_t *sih, uint bustype, void *curmap, osl_t *osh,
+ char **vars, uint *count) {
uint len;
len = 0;
@@ -189,8 +189,8 @@
/* support only 16-bit word read from srom */
int
-srom_read(si_t * sih, uint bustype, void *curmap, osl_t * osh,
- uint byteoff, uint nbytes, uint16 * buf, bool check_crc)
+srom_read(si_t *sih, uint bustype, void *curmap, osl_t *osh,
+ uint byteoff, uint nbytes, uint16 *buf, bool check_crc)
{
uint off, nw;
#ifdef BCMSDIO
@@ -377,8 +377,8 @@
#define BCMDONGLECASE(n)
int
-BCMATTACHFN(srom_parsecis) (osl_t * osh, uint8 * pcis[], uint ciscnt,
- char **vars, uint * count)
+BCMATTACHFN(srom_parsecis) (osl_t *osh, uint8 *pcis[], uint ciscnt,
+ char **vars, uint *count)
{
char eabuf[32];
char *base;
@@ -1411,7 +1411,7 @@
* not in the bus cores.
*/
static uint16
-srom_cc_cmd(si_t * sih, osl_t * osh, void *ccregs, uint32 cmd, uint wordoff,
+srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, uint32 cmd, uint wordoff,
uint16 data)
{
chipcregs_t *cc = (chipcregs_t *) ccregs;
@@ -1445,8 +1445,8 @@
* Return 0 on success, nonzero on error.
*/
static int
-sprom_read_pci(osl_t * osh, si_t * sih, uint16 * sprom, uint wordoff,
- uint16 * buf, uint nwords, bool check_crc)
+sprom_read_pci(osl_t *osh, si_t *sih, uint16 *sprom, uint wordoff,
+ uint16 *buf, uint nwords, bool check_crc)
{
int err = 0;
uint i;
@@ -1505,7 +1505,7 @@
}
#if defined(BCMNVRAMR)
-static int otp_read_pci(osl_t * osh, si_t * sih, uint16 * buf, uint bufsz)
+static int otp_read_pci(osl_t *osh, si_t *sih, uint16 *buf, uint bufsz)
{
uint8 *otp;
uint sz = OTP_SZ_MAX / 2; /* size in words */
@@ -1555,8 +1555,8 @@
* Return 0 on success, nonzero on error.
*/
static int
-BCMATTACHFN(initvars_table) (osl_t * osh, char *start, char *end, char **vars,
- uint * count) {
+BCMATTACHFN(initvars_table) (osl_t *osh, char *start, char *end, char **vars,
+ uint *count) {
int c = (int)(end - start);
/* do it only when there is more than just the null string */
@@ -1582,7 +1582,7 @@
* Return 0 on success, nonzero on error.
*/
static int
-BCMATTACHFN(initvars_flash) (si_t * sih, osl_t * osh, char **base, uint len) {
+BCMATTACHFN(initvars_flash) (si_t *sih, osl_t *osh, char **base, uint len) {
char *vp = *base;
char *flash;
int err;
@@ -1638,7 +1638,7 @@
* Return 0 on success, nonzero on error.
*/
static int
-BCMATTACHFN(initvars_flash_si) (si_t * sih, char **vars, uint * count) {
+BCMATTACHFN(initvars_flash_si) (si_t *sih, char **vars, uint *count) {
osl_t *osh = si_osh(sih);
char *vp, *base;
int err;
@@ -1697,8 +1697,8 @@
#endif /* BCMDBG */
static void
-BCMATTACHFN(_initvars_srom_pci) (uint8 sromrev, uint16 * srom, uint off,
- varbuf_t * b) {
+BCMATTACHFN(_initvars_srom_pci) (uint8 sromrev, uint16 *srom, uint off,
+ varbuf_t *b) {
uint16 w;
uint32 val;
const sromvar_t *srv;
@@ -1846,8 +1846,8 @@
* Return 0 on success, nonzero on error.
*/
static int
-BCMATTACHFN(initvars_srom_pci) (si_t * sih, void *curmap, char **vars,
- uint * count) {
+BCMATTACHFN(initvars_srom_pci) (si_t *sih, void *curmap, char **vars,
+ uint *count) {
uint16 *srom, *sromwindow;
uint8 sromrev = 0;
uint32 sr;
@@ -1992,7 +1992,7 @@
* Return 0 on success, nonzero on error.
*/
static int
-BCMATTACHFN(initvars_cis_sdio) (osl_t * osh, char **vars, uint * count) {
+BCMATTACHFN(initvars_cis_sdio) (osl_t *osh, char **vars, uint *count) {
uint8 *cis[SBSDIO_NUM_FUNCTION + 1];
uint fn, numfn;
int rc = 0;
@@ -2026,7 +2026,7 @@
}
/* set SDIO sprom command register */
-static int BCMATTACHFN(sprom_cmd_sdio) (osl_t * osh, uint8 cmd) {
+static int BCMATTACHFN(sprom_cmd_sdio) (osl_t *osh, uint8 cmd) {
uint8 status = 0;
uint wait_cnt = 1000;
@@ -2045,7 +2045,7 @@
}
/* read a word from the SDIO srom */
-static int sprom_read_sdio(osl_t * osh, uint16 addr, uint16 * data)
+static int sprom_read_sdio(osl_t *osh, uint16 addr, uint16 *data)
{
uint8 addr_l, addr_h, data_l, data_h;
@@ -2074,8 +2074,8 @@
#endif /* BCMSDIO */
static int
-BCMATTACHFN(initvars_srom_si) (si_t * sih, osl_t * osh, void *curmap,
- char **vars, uint * varsz) {
+BCMATTACHFN(initvars_srom_si) (si_t *sih, osl_t *osh, void *curmap,
+ char **vars, uint *varsz) {
/* Search flash nvram section for srom variables */
return initvars_flash_si(sih, vars, varsz);
}
diff --git a/drivers/staging/brcm80211/util/bcmutils.c b/drivers/staging/brcm80211/util/bcmutils.c
index c6c63a8..dc79705 100644
--- a/drivers/staging/brcm80211/util/bcmutils.c
+++ b/drivers/staging/brcm80211/util/bcmutils.c
@@ -34,7 +34,7 @@
#endif /* WLC_LOW */
/* copy a pkt buffer chain into a buffer */
-uint pktcopy(osl_t * osh, void *p, uint offset, int len, uchar * buf)
+uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf)
{
uint n, ret = 0;
@@ -65,7 +65,7 @@
}
/* copy a buffer into a pkt buffer chain */
-uint pktfrombuf(osl_t * osh, void *p, uint offset, int len, uchar * buf)
+uint pktfrombuf(osl_t *osh, void *p, uint offset, int len, uchar *buf)
{
uint n, ret = 0;
@@ -93,7 +93,7 @@
}
/* return total length of buffer chain */
-uint BCMFASTPATH pkttotlen(osl_t * osh, void *p)
+uint BCMFASTPATH pkttotlen(osl_t *osh, void *p)
{
uint total;
@@ -104,7 +104,7 @@
}
/* return the last buffer of chained pkt */
-void *pktlast(osl_t * osh, void *p)
+void *pktlast(osl_t *osh, void *p)
{
for (; PKTNEXT(p); p = PKTNEXT(p)) ;
@@ -112,7 +112,7 @@
}
/* count segments of a chained packet */
-uint BCMFASTPATH pktsegcnt(osl_t * osh, void *p)
+uint BCMFASTPATH pktsegcnt(osl_t *osh, void *p)
{
uint cnt;
@@ -234,7 +234,7 @@
}
void
-pktq_pflush(osl_t * osh, struct pktq *pq, int prec, bool dir, ifpkt_cb_t fn,
+pktq_pflush(osl_t *osh, struct pktq *pq, int prec, bool dir, ifpkt_cb_t fn,
int arg)
{
struct pktq_prec *q;
@@ -419,7 +419,7 @@
return (pq->q[prec].tail);
}
-void pktq_flush(osl_t * osh, struct pktq *pq, bool dir, ifpkt_cb_t fn, int arg)
+void pktq_flush(osl_t *osh, struct pktq *pq, bool dir, ifpkt_cb_t fn, int arg)
{
int prec;
for (prec = 0; prec < pq->num_prec; prec++)
@@ -778,7 +778,7 @@
}
/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
-int BCMROMFN(bcm_ether_atoe) (char *p, struct ether_addr * ea) {
+int BCMROMFN(bcm_ether_atoe) (char *p, struct ether_addr *ea) {
int i = 0;
for (;;) {
@@ -926,7 +926,7 @@
#if defined(BCMDBG)
/* pretty hex print a pkt buffer chain */
-void prpkt(const char *msg, osl_t * osh, void *p0)
+void prpkt(const char *msg, osl_t *osh, void *p0)
{
void *p;
@@ -983,7 +983,7 @@
vars_len = 0;
}
-char *bcm_nvram_vars(uint * length)
+char *bcm_nvram_vars(uint *length)
{
#ifndef BCMNVRAMR
/* cache may be stale if nvram is read/write */
@@ -1039,7 +1039,7 @@
#endif /* WLC_LOW */
/* iovar table lookup */
-const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t * table, const char *name)
+const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name)
{
const bcm_iovar_t *vi;
const char *lookup_name;
@@ -1062,7 +1062,7 @@
return NULL; /* var name not found */
}
-int bcm_iovar_lencheck(const bcm_iovar_t * vi, void *arg, int len, bool set)
+int bcm_iovar_lencheck(const bcm_iovar_t *vi, void *arg, int len, bool set)
{
int bcmerror = 0;
@@ -1167,7 +1167,7 @@
#define CRC_INNER_LOOP(n, c, x) \
(c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
-uint8 BCMROMFN(hndcrc8) (uint8 * pdata, /* pointer to array of data to process */
+uint8 BCMROMFN(hndcrc8) (uint8 *pdata, /* pointer to array of data to process */
uint nbytes, /* number of input data bytes to process */
uint8 crc /* either CRC8_INIT_VALUE or previous return value */
) {
@@ -1237,7 +1237,7 @@
0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78
};
-uint16 BCMROMFN(hndcrc16) (uint8 * pdata, /* pointer to array of data to process */
+uint16 BCMROMFN(hndcrc16) (uint8 *pdata, /* pointer to array of data to process */
uint nbytes, /* number of input data bytes to process */
uint16 crc /* either CRC16_INIT_VALUE or previous return value */
) {
@@ -1254,7 +1254,7 @@
* *buflen is not modified if the TLV elt parameter is invalid, or is decremented
* by the TLV parameter's length if it is valid.
*/
-bcm_tlv_t *BCMROMFN(bcm_next_tlv) (bcm_tlv_t * elt, int *buflen) {
+bcm_tlv_t *BCMROMFN(bcm_next_tlv) (bcm_tlv_t *elt, int *buflen) {
int len;
/* validate current elt */
@@ -1334,7 +1334,7 @@
#if defined(BCMDBG)
int
-bcm_format_flags(const bcm_bit_desc_t * bd, uint32 flags, char *buf, int len)
+bcm_format_flags(const bcm_bit_desc_t *bd, uint32 flags, char *buf, int len)
{
int i;
char *p = buf;
@@ -1402,7 +1402,7 @@
#endif /* defined(BCMDBG) */
/* pretty hex print a contiguous buffer */
-void prhex(const char *msg, uchar * buf, uint nbytes)
+void prhex(const char *msg, uchar *buf, uint nbytes)
{
char line[128], *p;
int len = sizeof(line);
@@ -1517,7 +1517,7 @@
/* routine to dump fields in a fileddesc structure */
uint
bcmdumpfields(bcmutl_rdreg_rtn read_rtn, void *arg0, uint arg1,
- struct fielddesc * fielddesc_array, char *buf, uint32 bufsize)
+ struct fielddesc *fielddesc_array, char *buf, uint32 bufsize)
{
uint filled_len;
int len;
@@ -1642,7 +1642,7 @@
return (qdbm);
}
-uint BCMROMFN(bcm_bitcount) (uint8 * bitmap, uint length) {
+uint BCMROMFN(bcm_bitcount) (uint8 *bitmap, uint length) {
uint bitcount = 0, i;
uint8 tmp;
for (i = 0; i < length; i++) {
@@ -1687,7 +1687,7 @@
return r;
}
-void bcm_inc_bytes(uchar * num, int num_bytes, uint8 amount)
+void bcm_inc_bytes(uchar *num, int num_bytes, uint8 amount)
{
int i;
@@ -1699,7 +1699,7 @@
}
}
-int bcm_cmp_bytes(uchar * arg1, uchar * arg2, uint8 nbytes)
+int bcm_cmp_bytes(uchar *arg1, uchar *arg2, uint8 nbytes)
{
int i;
@@ -1710,7 +1710,7 @@
return 0;
}
-void bcm_print_bytes(char *name, const uchar * data, int len)
+void bcm_print_bytes(char *name, const uchar *data, int len)
{
int i;
int per_line = 0;
diff --git a/drivers/staging/brcm80211/util/bcmwpa.c b/drivers/staging/brcm80211/util/bcmwpa.c
index d1b7c8d..29a4823 100644
--- a/drivers/staging/brcm80211/util/bcmwpa.c
+++ b/drivers/staging/brcm80211/util/bcmwpa.c
@@ -20,7 +20,7 @@
/* Is this body of this tlvs entry a WFA entry? If
* not update the tlvs buffer pointer/length.
*/
-bool bcm_is_wfa_ie(uint8 * ie, uint8 ** tlvs, uint * tlvs_len, uint8 type)
+bool bcm_is_wfa_ie(uint8 *ie, uint8 **tlvs, uint *tlvs_len, uint8 type)
{
/* If the contents match the WFA_OUI and type */
if ((ie[TLV_LEN_OFF] > (WFA_OUI_LEN + 1)) &&
diff --git a/drivers/staging/brcm80211/util/hnddma.c b/drivers/staging/brcm80211/util/hnddma.c
index 5b59ad8..4b642d6 100644
--- a/drivers/staging/brcm80211/util/hnddma.c
+++ b/drivers/staging/brcm80211/util/hnddma.c
@@ -180,83 +180,83 @@
#define PCI64ADDR_HIGH_SHIFT 31 /* address[63] */
/* Common prototypes */
-static bool _dma_isaddrext(dma_info_t * di);
-static bool _dma_descriptor_align(dma_info_t * di);
-static bool _dma_alloc(dma_info_t * di, uint direction);
-static void _dma_detach(dma_info_t * di);
-static void _dma_ddtable_init(dma_info_t * di, uint direction, dmaaddr_t pa);
-static void _dma_rxinit(dma_info_t * di);
-static void *_dma_rx(dma_info_t * di);
-static bool _dma_rxfill(dma_info_t * di);
-static void _dma_rxreclaim(dma_info_t * di);
-static void _dma_rxenable(dma_info_t * di);
-static void *_dma_getnextrxp(dma_info_t * di, bool forceall);
-static void _dma_rx_param_get(dma_info_t * di, uint16 * rxoffset,
- uint16 * rxbufsize);
+static bool _dma_isaddrext(dma_info_t *di);
+static bool _dma_descriptor_align(dma_info_t *di);
+static bool _dma_alloc(dma_info_t *di, uint direction);
+static void _dma_detach(dma_info_t *di);
+static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa);
+static void _dma_rxinit(dma_info_t *di);
+static void *_dma_rx(dma_info_t *di);
+static bool _dma_rxfill(dma_info_t *di);
+static void _dma_rxreclaim(dma_info_t *di);
+static void _dma_rxenable(dma_info_t *di);
+static void *_dma_getnextrxp(dma_info_t *di, bool forceall);
+static void _dma_rx_param_get(dma_info_t *di, uint16 *rxoffset,
+ uint16 *rxbufsize);
-static void _dma_txblock(dma_info_t * di);
-static void _dma_txunblock(dma_info_t * di);
-static uint _dma_txactive(dma_info_t * di);
-static uint _dma_rxactive(dma_info_t * di);
-static uint _dma_txpending(dma_info_t * di);
-static uint _dma_txcommitted(dma_info_t * di);
+static void _dma_txblock(dma_info_t *di);
+static void _dma_txunblock(dma_info_t *di);
+static uint _dma_txactive(dma_info_t *di);
+static uint _dma_rxactive(dma_info_t *di);
+static uint _dma_txpending(dma_info_t *di);
+static uint _dma_txcommitted(dma_info_t *di);
-static void *_dma_peeknexttxp(dma_info_t * di);
-static void *_dma_peeknextrxp(dma_info_t * di);
-static uintptr _dma_getvar(dma_info_t * di, const char *name);
-static void _dma_counterreset(dma_info_t * di);
-static void _dma_fifoloopbackenable(dma_info_t * di);
-static uint _dma_ctrlflags(dma_info_t * di, uint mask, uint flags);
+static void *_dma_peeknexttxp(dma_info_t *di);
+static void *_dma_peeknextrxp(dma_info_t *di);
+static uintptr _dma_getvar(dma_info_t *di, const char *name);
+static void _dma_counterreset(dma_info_t *di);
+static void _dma_fifoloopbackenable(dma_info_t *di);
+static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags);
static uint8 dma_align_sizetobits(uint size);
-static void *dma_ringalloc(osl_t * osh, uint32 boundary, uint size,
- uint16 * alignbits, uint * alloced,
- dmaaddr_t * descpa, osldma_t ** dmah);
+static void *dma_ringalloc(osl_t *osh, uint32 boundary, uint size,
+ uint16 *alignbits, uint *alloced,
+ dmaaddr_t *descpa, osldma_t **dmah);
/* Prototypes for 32-bit routines */
-static bool dma32_alloc(dma_info_t * di, uint direction);
-static bool dma32_txreset(dma_info_t * di);
-static bool dma32_rxreset(dma_info_t * di);
-static bool dma32_txsuspendedidle(dma_info_t * di);
-static int dma32_txfast(dma_info_t * di, void *p0, bool commit);
-static void *dma32_getnexttxp(dma_info_t * di, txd_range_t range);
-static void *dma32_getnextrxp(dma_info_t * di, bool forceall);
-static void dma32_txrotate(dma_info_t * di);
-static bool dma32_rxidle(dma_info_t * di);
-static void dma32_txinit(dma_info_t * di);
-static bool dma32_txenabled(dma_info_t * di);
-static void dma32_txsuspend(dma_info_t * di);
-static void dma32_txresume(dma_info_t * di);
-static bool dma32_txsuspended(dma_info_t * di);
-static void dma32_txreclaim(dma_info_t * di, txd_range_t range);
-static bool dma32_txstopped(dma_info_t * di);
-static bool dma32_rxstopped(dma_info_t * di);
-static bool dma32_rxenabled(dma_info_t * di);
+static bool dma32_alloc(dma_info_t *di, uint direction);
+static bool dma32_txreset(dma_info_t *di);
+static bool dma32_rxreset(dma_info_t *di);
+static bool dma32_txsuspendedidle(dma_info_t *di);
+static int dma32_txfast(dma_info_t *di, void *p0, bool commit);
+static void *dma32_getnexttxp(dma_info_t *di, txd_range_t range);
+static void *dma32_getnextrxp(dma_info_t *di, bool forceall);
+static void dma32_txrotate(dma_info_t *di);
+static bool dma32_rxidle(dma_info_t *di);
+static void dma32_txinit(dma_info_t *di);
+static bool dma32_txenabled(dma_info_t *di);
+static void dma32_txsuspend(dma_info_t *di);
+static void dma32_txresume(dma_info_t *di);
+static bool dma32_txsuspended(dma_info_t *di);
+static void dma32_txreclaim(dma_info_t *di, txd_range_t range);
+static bool dma32_txstopped(dma_info_t *di);
+static bool dma32_rxstopped(dma_info_t *di);
+static bool dma32_rxenabled(dma_info_t *di);
-static bool _dma32_addrext(osl_t * osh, dma32regs_t * dma32regs);
+static bool _dma32_addrext(osl_t *osh, dma32regs_t *dma32regs);
/* Prototypes for 64-bit routines */
-static bool dma64_alloc(dma_info_t * di, uint direction);
-static bool dma64_txreset(dma_info_t * di);
-static bool dma64_rxreset(dma_info_t * di);
-static bool dma64_txsuspendedidle(dma_info_t * di);
-static int dma64_txfast(dma_info_t * di, void *p0, bool commit);
-static int dma64_txunframed(dma_info_t * di, void *p0, uint len, bool commit);
-static void *dma64_getpos(dma_info_t * di, bool direction);
-static void *dma64_getnexttxp(dma_info_t * di, txd_range_t range);
-static void *dma64_getnextrxp(dma_info_t * di, bool forceall);
-static void dma64_txrotate(dma_info_t * di);
+static bool dma64_alloc(dma_info_t *di, uint direction);
+static bool dma64_txreset(dma_info_t *di);
+static bool dma64_rxreset(dma_info_t *di);
+static bool dma64_txsuspendedidle(dma_info_t *di);
+static int dma64_txfast(dma_info_t *di, void *p0, bool commit);
+static int dma64_txunframed(dma_info_t *di, void *p0, uint len, bool commit);
+static void *dma64_getpos(dma_info_t *di, bool direction);
+static void *dma64_getnexttxp(dma_info_t *di, txd_range_t range);
+static void *dma64_getnextrxp(dma_info_t *di, bool forceall);
+static void dma64_txrotate(dma_info_t *di);
-static bool dma64_rxidle(dma_info_t * di);
-static void dma64_txinit(dma_info_t * di);
-static bool dma64_txenabled(dma_info_t * di);
-static void dma64_txsuspend(dma_info_t * di);
-static void dma64_txresume(dma_info_t * di);
-static bool dma64_txsuspended(dma_info_t * di);
-static void dma64_txreclaim(dma_info_t * di, txd_range_t range);
-static bool dma64_txstopped(dma_info_t * di);
-static bool dma64_rxstopped(dma_info_t * di);
-static bool dma64_rxenabled(dma_info_t * di);
-static bool _dma64_addrext(osl_t * osh, dma64regs_t * dma64regs);
+static bool dma64_rxidle(dma_info_t *di);
+static void dma64_txinit(dma_info_t *di);
+static bool dma64_txenabled(dma_info_t *di);
+static void dma64_txsuspend(dma_info_t *di);
+static void dma64_txresume(dma_info_t *di);
+static bool dma64_txsuspended(dma_info_t *di);
+static void dma64_txreclaim(dma_info_t *di, txd_range_t range);
+static bool dma64_txstopped(dma_info_t *di);
+static bool dma64_rxstopped(dma_info_t *di);
+static bool dma64_rxenabled(dma_info_t *di);
+static bool _dma64_addrext(osl_t *osh, dma64regs_t *dma64regs);
STATIC INLINE uint32 parity32(uint32 data);
@@ -354,10 +354,10 @@
39
};
-hnddma_t *dma_attach(osl_t * osh, char *name, si_t * sih, void *dmaregstx,
+hnddma_t *dma_attach(osl_t *osh, char *name, si_t *sih, void *dmaregstx,
void *dmaregsrx, uint ntxd, uint nrxd, uint rxbufsize,
int rxextheadroom, uint nrxpost, uint rxoffset,
- uint * msg_level)
+ uint *msg_level)
{
dma_info_t *di;
uint size;
@@ -569,8 +569,8 @@
/* init the tx or rx descriptor */
static INLINE void
-dma32_dd_upd(dma_info_t * di, dma32dd_t * ddring, dmaaddr_t pa, uint outidx,
- uint32 * flags, uint32 bufcount)
+dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, dmaaddr_t pa, uint outidx,
+ uint32 *flags, uint32 bufcount)
{
/* dma32 uses 32-bit control to fit both flags and bufcounter */
*flags = *flags | (bufcount & CTRL_BC_MASK);
@@ -608,8 +608,8 @@
#define DMA64_DD_PARITY(dd) parity32((dd)->addrlow ^ (dd)->addrhigh ^ (dd)->ctrl1 ^ (dd)->ctrl2)
static INLINE void
-dma64_dd_upd(dma_info_t * di, dma64dd_t * ddring, dmaaddr_t pa, uint outidx,
- uint32 * flags, uint32 bufcount)
+dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, dmaaddr_t pa, uint outidx,
+ uint32 *flags, uint32 bufcount)
{
uint32 ctrl2 = bufcount & D64_CTRL2_BC_MASK;
@@ -653,7 +653,7 @@
}
}
-static bool _dma32_addrext(osl_t * osh, dma32regs_t * dma32regs)
+static bool _dma32_addrext(osl_t *osh, dma32regs_t *dma32regs)
{
uint32 w;
@@ -663,7 +663,7 @@
return ((w & XC_AE) == XC_AE);
}
-static bool _dma_alloc(dma_info_t * di, uint direction)
+static bool _dma_alloc(dma_info_t *di, uint direction)
{
if (DMA64_ENAB(di) && DMA64_MODE(di)) {
return dma64_alloc(di, direction);
@@ -674,7 +674,7 @@
}
/* !! may be called with core in reset */
-static void _dma_detach(dma_info_t * di)
+static void _dma_detach(dma_info_t *di)
{
DMA_TRACE(("%s: dma_detach\n", di->name));
@@ -730,7 +730,7 @@
}
-static bool _dma_descriptor_align(dma_info_t * di)
+static bool _dma_descriptor_align(dma_info_t *di)
{
if (DMA64_ENAB(di) && DMA64_MODE(di)) {
uint32 addrl;
@@ -752,7 +752,7 @@
}
/* return TRUE if this dma engine supports DmaExtendedAddrChanges, otherwise FALSE */
-static bool _dma_isaddrext(dma_info_t * di)
+static bool _dma_isaddrext(dma_info_t *di)
{
if (DMA64_ENAB(di) && DMA64_MODE(di)) {
/* DMA64 supports full 32- or 64-bit operation. AE is always valid */
@@ -784,7 +784,7 @@
}
/* initialize descriptor table base address */
-static void _dma_ddtable_init(dma_info_t * di, uint direction, dmaaddr_t pa)
+static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa)
{
if (DMA64_ENAB(di) && DMA64_MODE(di)) {
if (!di->aligndesc_4k) {
@@ -871,7 +871,7 @@
ASSERT(0);
}
-static void _dma_fifoloopbackenable(dma_info_t * di)
+static void _dma_fifoloopbackenable(dma_info_t *di)
{
DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
@@ -883,7 +883,7 @@
ASSERT(0);
}
-static void _dma_rxinit(dma_info_t * di)
+static void _dma_rxinit(dma_info_t *di)
{
DMA_TRACE(("%s: dma_rxinit\n", di->name));
@@ -916,7 +916,7 @@
ASSERT(0);
}
-static void _dma_rxenable(dma_info_t * di)
+static void _dma_rxenable(dma_info_t *di)
{
uint dmactrlflags = di->hnddma.dmactrlflags;
@@ -952,7 +952,7 @@
}
static void
-_dma_rx_param_get(dma_info_t * di, uint16 * rxoffset, uint16 * rxbufsize)
+_dma_rx_param_get(dma_info_t *di, uint16 *rxoffset, uint16 *rxbufsize)
{
/* the normal values fit into 16 bits */
*rxoffset = (uint16) di->rxoffset;
@@ -968,7 +968,7 @@
* After it reaches the max size of buffer, the data continues in next DMA descriptor
* buffer WITHOUT DMA header
*/
-static void *BCMFASTPATH _dma_rx(dma_info_t * di)
+static void *BCMFASTPATH _dma_rx(dma_info_t *di)
{
void *p, *head, *tail;
uint len;
@@ -1043,7 +1043,7 @@
* this will stall the rx dma and user might want to call rxfill again asap
* This unlikely happens on memory-rich NIC, but often on memory-constrained dongle
*/
-static bool BCMFASTPATH _dma_rxfill(dma_info_t * di)
+static bool BCMFASTPATH _dma_rxfill(dma_info_t *di)
{
void *p;
uint16 rxin, rxout;
@@ -1155,7 +1155,7 @@
}
/* like getnexttxp but no reclaim */
-static void *_dma_peeknexttxp(dma_info_t * di)
+static void *_dma_peeknexttxp(dma_info_t *di)
{
uint end, i;
@@ -1182,7 +1182,7 @@
}
/* like getnextrxp but not take off the ring */
-static void *_dma_peeknextrxp(dma_info_t * di)
+static void *_dma_peeknextrxp(dma_info_t *di)
{
uint end, i;
@@ -1208,7 +1208,7 @@
return (NULL);
}
-static void _dma_rxreclaim(dma_info_t * di)
+static void _dma_rxreclaim(dma_info_t *di)
{
void *p;
@@ -1223,7 +1223,7 @@
PKTFREE(di->osh, p, FALSE);
}
-static void *BCMFASTPATH _dma_getnextrxp(dma_info_t * di, bool forceall)
+static void *BCMFASTPATH _dma_getnextrxp(dma_info_t *di, bool forceall)
{
if (di->nrxd == 0)
return (NULL);
@@ -1236,22 +1236,22 @@
ASSERT(0);
}
-static void _dma_txblock(dma_info_t * di)
+static void _dma_txblock(dma_info_t *di)
{
di->hnddma.txavail = 0;
}
-static void _dma_txunblock(dma_info_t * di)
+static void _dma_txunblock(dma_info_t *di)
{
di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
}
-static uint _dma_txactive(dma_info_t * di)
+static uint _dma_txactive(dma_info_t *di)
{
return NTXDACTIVE(di->txin, di->txout);
}
-static uint _dma_txpending(dma_info_t * di)
+static uint _dma_txpending(dma_info_t *di)
{
uint curr;
@@ -1270,7 +1270,7 @@
return NTXDACTIVE(curr, di->txout);
}
-static uint _dma_txcommitted(dma_info_t * di)
+static uint _dma_txcommitted(dma_info_t *di)
{
uint ptr;
uint txin = di->txin;
@@ -1288,12 +1288,12 @@
return NTXDACTIVE(di->txin, ptr);
}
-static uint _dma_rxactive(dma_info_t * di)
+static uint _dma_rxactive(dma_info_t *di)
{
return NRXDACTIVE(di->rxin, di->rxout);
}
-static void _dma_counterreset(dma_info_t * di)
+static void _dma_counterreset(dma_info_t *di)
{
/* reset all software counter */
di->hnddma.rxgiants = 0;
@@ -1301,7 +1301,7 @@
di->hnddma.txnobuf = 0;
}
-static uint _dma_ctrlflags(dma_info_t * di, uint mask, uint flags)
+static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags)
{
uint dmactrlflags = di->hnddma.dmactrlflags;
@@ -1354,7 +1354,7 @@
}
/* get the address of the var in order to change later */
-static uintptr _dma_getvar(dma_info_t * di, const char *name)
+static uintptr _dma_getvar(dma_info_t *di, const char *name)
{
if (!strcmp(name, "&txavail"))
return ((uintptr) & (di->hnddma.txavail));
@@ -1364,7 +1364,7 @@
return (0);
}
-void dma_txpioloopback(osl_t * osh, dma32regs_t * regs)
+void dma_txpioloopback(osl_t *osh, dma32regs_t *regs)
{
OR_REG(osh, ®s->control, XC_LE);
}
@@ -1387,9 +1387,9 @@
* descriptor ring size aligned location. This will ensure that the ring will
* not cross page boundary
*/
-static void *dma_ringalloc(osl_t * osh, uint32 boundary, uint size,
- uint16 * alignbits, uint * alloced,
- dmaaddr_t * descpa, osldma_t ** dmah)
+static void *dma_ringalloc(osl_t *osh, uint32 boundary, uint size,
+ uint16 *alignbits, uint *alloced,
+ dmaaddr_t *descpa, osldma_t **dmah)
{
void *va;
uint32 desc_strtaddr;
@@ -1414,7 +1414,7 @@
/* 32-bit DMA functions */
-static void dma32_txinit(dma_info_t * di)
+static void dma32_txinit(dma_info_t *di)
{
uint32 control = XC_XE;
@@ -1435,7 +1435,7 @@
_dma_ddtable_init(di, DMA_TX, di->txdpa);
}
-static bool dma32_txenabled(dma_info_t * di)
+static bool dma32_txenabled(dma_info_t *di)
{
uint32 xc;
@@ -1444,7 +1444,7 @@
return ((xc != 0xffffffff) && (xc & XC_XE));
}
-static void dma32_txsuspend(dma_info_t * di)
+static void dma32_txsuspend(dma_info_t *di)
{
DMA_TRACE(("%s: dma_txsuspend\n", di->name));
@@ -1454,7 +1454,7 @@
OR_REG(di->osh, &di->d32txregs->control, XC_SE);
}
-static void dma32_txresume(dma_info_t * di)
+static void dma32_txresume(dma_info_t *di)
{
DMA_TRACE(("%s: dma_txresume\n", di->name));
@@ -1464,13 +1464,13 @@
AND_REG(di->osh, &di->d32txregs->control, ~XC_SE);
}
-static bool dma32_txsuspended(dma_info_t * di)
+static bool dma32_txsuspended(dma_info_t *di)
{
return (di->ntxd == 0)
|| ((R_REG(di->osh, &di->d32txregs->control) & XC_SE) == XC_SE);
}
-static void dma32_txreclaim(dma_info_t * di, txd_range_t range)
+static void dma32_txreclaim(dma_info_t *di, txd_range_t range)
{
void *p;
@@ -1487,19 +1487,19 @@
PKTFREE(di->osh, p, TRUE);
}
-static bool dma32_txstopped(dma_info_t * di)
+static bool dma32_txstopped(dma_info_t *di)
{
return ((R_REG(di->osh, &di->d32txregs->status) & XS_XS_MASK) ==
XS_XS_STOPPED);
}
-static bool dma32_rxstopped(dma_info_t * di)
+static bool dma32_rxstopped(dma_info_t *di)
{
return ((R_REG(di->osh, &di->d32rxregs->status) & RS_RS_MASK) ==
RS_RS_STOPPED);
}
-static bool dma32_alloc(dma_info_t * di, uint direction)
+static bool dma32_alloc(dma_info_t *di, uint direction)
{
uint size;
uint ddlen;
@@ -1564,7 +1564,7 @@
return TRUE;
}
-static bool dma32_txreset(dma_info_t * di)
+static bool dma32_txreset(dma_info_t *di)
{
uint32 status;
@@ -1589,7 +1589,7 @@
return (status == XS_XS_DISABLED);
}
-static bool dma32_rxidle(dma_info_t * di)
+static bool dma32_rxidle(dma_info_t *di)
{
DMA_TRACE(("%s: dma_rxidle\n", di->name));
@@ -1600,7 +1600,7 @@
R_REG(di->osh, &di->d32rxregs->ptr));
}
-static bool dma32_rxreset(dma_info_t * di)
+static bool dma32_rxreset(dma_info_t *di)
{
uint32 status;
@@ -1615,7 +1615,7 @@
return (status == RS_RS_DISABLED);
}
-static bool dma32_rxenabled(dma_info_t * di)
+static bool dma32_rxenabled(dma_info_t *di)
{
uint32 rc;
@@ -1623,7 +1623,7 @@
return ((rc != 0xffffffff) && (rc & RC_RE));
}
-static bool dma32_txsuspendedidle(dma_info_t * di)
+static bool dma32_txsuspendedidle(dma_info_t *di)
{
if (di->ntxd == 0)
return TRUE;
@@ -1646,7 +1646,7 @@
* WARNING: call must check the return value for error.
* the error(toss frames) could be fatal and cause many subsequent hard to debug problems
*/
-static int dma32_txfast(dma_info_t * di, void *p0, bool commit)
+static int dma32_txfast(dma_info_t *di, void *p0, bool commit)
{
void *p, *next;
uchar *data;
@@ -1772,7 +1772,7 @@
* If range is HNDDMA_RANGE_ALL, reclaim all txd(s) posted to the ring and
* return associated packet regardless of the value of hardware pointers.
*/
-static void *dma32_getnexttxp(dma_info_t * di, txd_range_t range)
+static void *dma32_getnexttxp(dma_info_t *di, txd_range_t range)
{
uint16 start, end, i;
uint16 active_desc;
@@ -1857,7 +1857,7 @@
return (NULL);
}
-static void *dma32_getnextrxp(dma_info_t * di, bool forceall)
+static void *dma32_getnextrxp(dma_info_t *di, bool forceall)
{
uint i, curr;
void *rxp;
@@ -1901,7 +1901,7 @@
/*
* Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
*/
-static void dma32_txrotate(dma_info_t * di)
+static void dma32_txrotate(dma_info_t *di)
{
uint16 ad;
uint nactive;
@@ -1971,7 +1971,7 @@
/* 64-bit DMA functions */
-static void dma64_txinit(dma_info_t * di)
+static void dma64_txinit(dma_info_t *di)
{
uint32 control = D64_XC_XE;
@@ -2003,7 +2003,7 @@
_dma_ddtable_init(di, DMA_TX, di->txdpa);
}
-static bool dma64_txenabled(dma_info_t * di)
+static bool dma64_txenabled(dma_info_t *di)
{
uint32 xc;
@@ -2012,7 +2012,7 @@
return ((xc != 0xffffffff) && (xc & D64_XC_XE));
}
-static void dma64_txsuspend(dma_info_t * di)
+static void dma64_txsuspend(dma_info_t *di)
{
DMA_TRACE(("%s: dma_txsuspend\n", di->name));
@@ -2022,7 +2022,7 @@
OR_REG(di->osh, &di->d64txregs->control, D64_XC_SE);
}
-static void dma64_txresume(dma_info_t * di)
+static void dma64_txresume(dma_info_t *di)
{
DMA_TRACE(("%s: dma_txresume\n", di->name));
@@ -2032,14 +2032,14 @@
AND_REG(di->osh, &di->d64txregs->control, ~D64_XC_SE);
}
-static bool dma64_txsuspended(dma_info_t * di)
+static bool dma64_txsuspended(dma_info_t *di)
{
return (di->ntxd == 0) ||
((R_REG(di->osh, &di->d64txregs->control) & D64_XC_SE) ==
D64_XC_SE);
}
-static void BCMFASTPATH dma64_txreclaim(dma_info_t * di, txd_range_t range)
+static void BCMFASTPATH dma64_txreclaim(dma_info_t *di, txd_range_t range)
{
void *p;
@@ -2059,19 +2059,19 @@
}
}
-static bool dma64_txstopped(dma_info_t * di)
+static bool dma64_txstopped(dma_info_t *di)
{
return ((R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_XS_MASK) ==
D64_XS0_XS_STOPPED);
}
-static bool dma64_rxstopped(dma_info_t * di)
+static bool dma64_rxstopped(dma_info_t *di)
{
return ((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_RS_MASK) ==
D64_RS0_RS_STOPPED);
}
-static bool dma64_alloc(dma_info_t * di, uint direction)
+static bool dma64_alloc(dma_info_t *di, uint direction)
{
uint16 size;
uint ddlen;
@@ -2131,7 +2131,7 @@
return TRUE;
}
-static bool dma64_txreset(dma_info_t * di)
+static bool dma64_txreset(dma_info_t *di)
{
uint32 status;
@@ -2156,7 +2156,7 @@
return (status == D64_XS0_XS_DISABLED);
}
-static bool dma64_rxidle(dma_info_t * di)
+static bool dma64_rxidle(dma_info_t *di)
{
DMA_TRACE(("%s: dma_rxidle\n", di->name));
@@ -2167,7 +2167,7 @@
(R_REG(di->osh, &di->d64rxregs->ptr) & D64_RS0_CD_MASK));
}
-static bool dma64_rxreset(dma_info_t * di)
+static bool dma64_rxreset(dma_info_t *di)
{
uint32 status;
@@ -2182,7 +2182,7 @@
return (status == D64_RS0_RS_DISABLED);
}
-static bool dma64_rxenabled(dma_info_t * di)
+static bool dma64_rxenabled(dma_info_t *di)
{
uint32 rc;
@@ -2190,7 +2190,7 @@
return ((rc != 0xffffffff) && (rc & D64_RC_RE));
}
-static bool dma64_txsuspendedidle(dma_info_t * di)
+static bool dma64_txsuspendedidle(dma_info_t *di)
{
if (di->ntxd == 0)
@@ -2210,7 +2210,7 @@
* We return a pointer to the beginning of the DATA buffer of the current descriptor.
* If DMA is idle, we return NULL.
*/
-static void *dma64_getpos(dma_info_t * di, bool direction)
+static void *dma64_getpos(dma_info_t *di, bool direction)
{
void *va;
bool idle;
@@ -2245,7 +2245,7 @@
* Each call to this is results in a single descriptor being added for "len" bytes of
* data starting at "buf", it doesn't handle chained buffers.
*/
-static int dma64_txunframed(dma_info_t * di, void *buf, uint len, bool commit)
+static int dma64_txunframed(dma_info_t *di, void *buf, uint len, bool commit)
{
uint16 txout;
uint32 flags = 0;
@@ -2299,7 +2299,7 @@
* WARNING: call must check the return value for error.
* the error(toss frames) could be fatal and cause many subsequent hard to debug problems
*/
-static int BCMFASTPATH dma64_txfast(dma_info_t * di, void *p0, bool commit)
+static int BCMFASTPATH dma64_txfast(dma_info_t *di, void *p0, bool commit)
{
void *p, *next;
uchar *data;
@@ -2424,7 +2424,7 @@
* If range is HNDDMA_RANGE_ALL, reclaim all txd(s) posted to the ring and
* return associated packet regardless of the value of hardware pointers.
*/
-static void *BCMFASTPATH dma64_getnexttxp(dma_info_t * di, txd_range_t range)
+static void *BCMFASTPATH dma64_getnexttxp(dma_info_t *di, txd_range_t range)
{
uint16 start, end, i;
uint16 active_desc;
@@ -2516,7 +2516,7 @@
return (NULL);
}
-static void *BCMFASTPATH dma64_getnextrxp(dma_info_t * di, bool forceall)
+static void *BCMFASTPATH dma64_getnextrxp(dma_info_t *di, bool forceall)
{
uint i, curr;
void *rxp;
@@ -2562,7 +2562,7 @@
return (rxp);
}
-static bool _dma64_addrext(osl_t * osh, dma64regs_t * dma64regs)
+static bool _dma64_addrext(osl_t *osh, dma64regs_t * dma64regs)
{
uint32 w;
OR_REG(osh, &dma64regs->control, D64_XC_AE);
@@ -2574,7 +2574,7 @@
/*
* Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
*/
-static void dma64_txrotate(dma_info_t * di)
+static void dma64_txrotate(dma_info_t *di)
{
uint16 ad;
uint nactive;
@@ -2650,7 +2650,7 @@
di->xmtptrbase + I2B(di->txout, dma64dd_t));
}
-uint dma_addrwidth(si_t * sih, void *dmaregs)
+uint dma_addrwidth(si_t *sih, void *dmaregs)
{
dma32regs_t *dma32regs;
osl_t *osh;
diff --git a/drivers/staging/brcm80211/util/hndpmu.c b/drivers/staging/brcm80211/util/hndpmu.c
index 5fca01e..e0d54d9 100644
--- a/drivers/staging/brcm80211/util/hndpmu.c
+++ b/drivers/staging/brcm80211/util/hndpmu.c
@@ -39,25 +39,25 @@
#define PMU_NONE(args)
/* PLL controls/clocks */
-static void si_pmu1_pllinit0(si_t * sih, osl_t * osh, chipcregs_t * cc,
+static void si_pmu1_pllinit0(si_t *sih, osl_t *osh, chipcregs_t *cc,
uint32 xtal);
-static uint32 si_pmu1_cpuclk0(si_t * sih, osl_t * osh, chipcregs_t * cc);
-static uint32 si_pmu1_alpclk0(si_t * sih, osl_t * osh, chipcregs_t * cc);
+static uint32 si_pmu1_cpuclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
+static uint32 si_pmu1_alpclk0(si_t *sih, osl_t *osh, chipcregs_t *cc);
/* PMU resources */
-static bool si_pmu_res_depfltr_bb(si_t * sih);
-static bool si_pmu_res_depfltr_ncb(si_t * sih);
-static bool si_pmu_res_depfltr_paldo(si_t * sih);
-static bool si_pmu_res_depfltr_npaldo(si_t * sih);
-static uint32 si_pmu_res_deps(si_t * sih, osl_t * osh, chipcregs_t * cc,
+static bool si_pmu_res_depfltr_bb(si_t *sih);
+static bool si_pmu_res_depfltr_ncb(si_t *sih);
+static bool si_pmu_res_depfltr_paldo(si_t *sih);
+static bool si_pmu_res_depfltr_npaldo(si_t *sih);
+static uint32 si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc,
uint32 rsrcs, bool all);
-static uint si_pmu_res_uptime(si_t * sih, osl_t * osh, chipcregs_t * cc,
+static uint si_pmu_res_uptime(si_t *sih, osl_t *osh, chipcregs_t *cc,
uint8 rsrc);
-static void si_pmu_res_masks(si_t * sih, uint32 * pmin, uint32 * pmax);
-static void si_pmu_spuravoid_pllupdate(si_t * sih, chipcregs_t * cc,
- osl_t * osh, uint8 spuravoid);
+static void si_pmu_res_masks(si_t *sih, uint32 * pmin, uint32 * pmax);
+static void si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc,
+ osl_t *osh, uint8 spuravoid);
-static void si_pmu_set_4330_plldivs(si_t * sih);
+static void si_pmu_set_4330_plldivs(si_t *sih);
/* FVCO frequency */
#define FVCO_880 880000 /* 880MHz */
@@ -66,7 +66,7 @@
#define FVCO_960 960000 /* 960MHz */
/* Read/write a chipcontrol reg */
-uint32 si_pmu_chipcontrol(si_t * sih, uint reg, uint32 mask, uint32 val)
+uint32 si_pmu_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val)
{
si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol_addr), ~0,
reg);
@@ -75,7 +75,7 @@
}
/* Read/write a regcontrol reg */
-uint32 si_pmu_regcontrol(si_t * sih, uint reg, uint32 mask, uint32 val)
+uint32 si_pmu_regcontrol(si_t *sih, uint reg, uint32 mask, uint32 val)
{
si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, regcontrol_addr), ~0,
reg);
@@ -84,7 +84,7 @@
}
/* Read/write a pllcontrol reg */
-uint32 si_pmu_pllcontrol(si_t * sih, uint reg, uint32 mask, uint32 val)
+uint32 si_pmu_pllcontrol(si_t *sih, uint reg, uint32 mask, uint32 val)
{
si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, pllcontrol_addr), ~0,
reg);
@@ -93,7 +93,7 @@
}
/* PMU PLL update */
-void si_pmu_pllupd(si_t * sih)
+void si_pmu_pllupd(si_t *sih)
{
si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, pmucontrol),
PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
@@ -101,7 +101,7 @@
/* Setup switcher voltage */
void
-BCMATTACHFN(si_pmu_set_switcher_voltage) (si_t * sih, osl_t * osh,
+BCMATTACHFN(si_pmu_set_switcher_voltage) (si_t *sih, osl_t *osh,
uint8 bb_voltage, uint8 rf_voltage) {
chipcregs_t *cc;
uint origidx;
@@ -124,7 +124,7 @@
}
void
-BCMATTACHFN(si_pmu_set_ldo_voltage) (si_t * sih, osl_t * osh, uint8 ldo,
+BCMATTACHFN(si_pmu_set_ldo_voltage) (si_t *sih, osl_t *osh, uint8 ldo,
uint8 voltage) {
uint8 sr_cntl_shift = 0, rc_shift = 0, shift = 0, mask = 0;
uint8 addr = 0;
@@ -182,7 +182,7 @@
/* d11 slow to fast clock transition time in slow clock cycles */
#define D11SCC_SLOW2FAST_TRANSITION 2
-uint16 BCMINITFN(si_pmu_fast_pwrup_delay) (si_t * sih, osl_t * osh) {
+uint16 BCMINITFN(si_pmu_fast_pwrup_delay) (si_t *sih, osl_t *osh) {
uint delay = PMU_MAX_TRANSITION_DLY;
chipcregs_t *cc;
uint origidx;
@@ -258,7 +258,7 @@
return (uint16) delay;
}
-uint32 BCMATTACHFN(si_pmu_force_ilp) (si_t * sih, osl_t * osh, bool force) {
+uint32 BCMATTACHFN(si_pmu_force_ilp) (si_t *sih, osl_t *osh, bool force) {
chipcregs_t *cc;
uint origidx;
uint32 oldpmucontrol;
@@ -295,7 +295,7 @@
uint32 res_mask; /* resources (chip specific) */
int8 action; /* action */
uint32 depend_mask; /* changes to the dependancies mask */
- bool(*filter) (si_t * sih); /* action is taken when filter is NULL or return TRUE */
+ bool(*filter) (si_t *sih); /* action is taken when filter is NULL or return TRUE */
} pmu_res_depend_t;
/* Resource dependancies mask change action */
@@ -578,23 +578,23 @@
};
/* TRUE if the power topology uses the buck boost to provide 3.3V to VDDIO_RF and WLAN PA */
-static bool BCMATTACHFN(si_pmu_res_depfltr_bb) (si_t * sih) {
+static bool BCMATTACHFN(si_pmu_res_depfltr_bb) (si_t *sih) {
return (sih->boardflags & BFL_BUCKBOOST) != 0;
}
/* TRUE if the power topology doesn't use the cbuck. Key on chiprev also if the chip is BCM4325. */
-static bool BCMATTACHFN(si_pmu_res_depfltr_ncb) (si_t * sih) {
+static bool BCMATTACHFN(si_pmu_res_depfltr_ncb) (si_t *sih) {
return ((sih->boardflags & BFL_NOCBUCK) != 0);
}
/* TRUE if the power topology uses the PALDO */
-static bool BCMATTACHFN(si_pmu_res_depfltr_paldo) (si_t * sih) {
+static bool BCMATTACHFN(si_pmu_res_depfltr_paldo) (si_t *sih) {
return (sih->boardflags & BFL_PALDO) != 0;
}
/* TRUE if the power topology doesn't use the PALDO */
-static bool BCMATTACHFN(si_pmu_res_depfltr_npaldo) (si_t * sih) {
+static bool BCMATTACHFN(si_pmu_res_depfltr_npaldo) (si_t *sih) {
return (sih->boardflags & BFL_PALDO) == 0;
}
@@ -602,7 +602,7 @@
sih->boardtype == BCM94325BGABU_BOARD)
/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */
-static void si_pmu_res_masks(si_t * sih, uint32 * pmin, uint32 * pmax)
+static void si_pmu_res_masks(si_t *sih, uint32 * pmin, uint32 * pmax)
{
uint32 min_mask = 0, max_mask = 0;
uint rsrcs;
@@ -688,7 +688,7 @@
}
/* initialize PMU resources */
-void BCMATTACHFN(si_pmu_res_init) (si_t * sih, osl_t * osh) {
+void BCMATTACHFN(si_pmu_res_init) (si_t *sih, osl_t *osh) {
chipcregs_t *cc;
uint origidx;
const pmu_res_updown_t *pmu_res_updown_table = NULL;
@@ -1104,7 +1104,7 @@
#define PMU1_XTALTAB0_960_48000K 15
/* select xtal table for each chip */
-static const pmu1_xtaltab0_t *BCMINITFN(si_pmu1_xtaltab0) (si_t * sih) {
+static const pmu1_xtaltab0_t *BCMINITFN(si_pmu1_xtaltab0) (si_t *sih) {
#ifdef BCMDBG
char chn[8];
#endif
@@ -1130,7 +1130,7 @@
}
/* select default xtal frequency for each chip */
-static const pmu1_xtaltab0_t *BCMINITFN(si_pmu1_xtaldef0) (si_t * sih) {
+static const pmu1_xtaltab0_t *BCMINITFN(si_pmu1_xtaldef0) (si_t *sih) {
#ifdef BCMDBG
char chn[8];
#endif
@@ -1161,7 +1161,7 @@
}
/* select default pll fvco for each chip */
-static uint32 BCMINITFN(si_pmu1_pllfvco0) (si_t * sih) {
+static uint32 BCMINITFN(si_pmu1_pllfvco0) (si_t *sih) {
#ifdef BCMDBG
char chn[8];
#endif
@@ -1189,7 +1189,7 @@
/* query alp/xtal clock frequency */
static uint32
-BCMINITFN(si_pmu1_alpclk0) (si_t * sih, osl_t * osh, chipcregs_t * cc) {
+BCMINITFN(si_pmu1_alpclk0) (si_t *sih, osl_t *osh, chipcregs_t *cc) {
const pmu1_xtaltab0_t *xt;
uint32 xf;
@@ -1214,7 +1214,7 @@
* si_pmu1_xtaldef0() wherever it is needed to return a default value.
*/
static void
-BCMATTACHFN(si_pmu1_pllinit0) (si_t * sih, osl_t * osh, chipcregs_t * cc,
+BCMATTACHFN(si_pmu1_pllinit0) (si_t *sih, osl_t *osh, chipcregs_t *cc,
uint32 xtal) {
const pmu1_xtaltab0_t *xt;
uint32 tmp;
@@ -1459,7 +1459,7 @@
/* query the CPU clock frequency */
static uint32
-BCMINITFN(si_pmu1_cpuclk0) (si_t * sih, osl_t * osh, chipcregs_t * cc) {
+BCMINITFN(si_pmu1_cpuclk0) (si_t *sih, osl_t *osh, chipcregs_t *cc) {
uint32 tmp, m1div;
#ifdef BCMDBG
uint32 ndiv_int, ndiv_frac, p2div, p1div, fvco;
@@ -1512,7 +1512,7 @@
}
/* initialize PLL */
-void BCMATTACHFN(si_pmu_pll_init) (si_t * sih, osl_t * osh, uint xtalfreq) {
+void BCMATTACHFN(si_pmu_pll_init) (si_t *sih, osl_t *osh, uint xtalfreq) {
chipcregs_t *cc;
uint origidx;
#ifdef BCMDBG
@@ -1564,7 +1564,7 @@
}
/* query alp/xtal clock frequency */
-uint32 BCMINITFN(si_pmu_alp_clock) (si_t * sih, osl_t * osh) {
+uint32 BCMINITFN(si_pmu_alp_clock) (si_t *sih, osl_t *osh) {
chipcregs_t *cc;
uint origidx;
uint32 clock = ALP_CLOCK;
@@ -1624,7 +1624,7 @@
* pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
*/
static uint32
-BCMINITFN(si_pmu5_clock) (si_t * sih, osl_t * osh, chipcregs_t * cc, uint pll0,
+BCMINITFN(si_pmu5_clock) (si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0,
uint m) {
uint32 tmp, div, ndiv, p1, p2, fc;
@@ -1677,7 +1677,7 @@
/* For designs that feed the same clock to both backplane
* and CPU just return the CPU clock speed.
*/
-uint32 BCMINITFN(si_pmu_si_clock) (si_t * sih, osl_t * osh) {
+uint32 BCMINITFN(si_pmu_si_clock) (si_t *sih, osl_t *osh) {
chipcregs_t *cc;
uint origidx;
uint32 clock = HT_CLOCK;
@@ -1755,7 +1755,7 @@
}
/* query CPU clock frequency */
-uint32 BCMINITFN(si_pmu_cpu_clock) (si_t * sih, osl_t * osh) {
+uint32 BCMINITFN(si_pmu_cpu_clock) (si_t *sih, osl_t *osh) {
chipcregs_t *cc;
uint origidx;
uint32 clock;
@@ -1798,7 +1798,7 @@
}
/* query memory clock frequency */
-uint32 BCMINITFN(si_pmu_mem_clock) (si_t * sih, osl_t * osh) {
+uint32 BCMINITFN(si_pmu_mem_clock) (si_t *sih, osl_t *osh) {
chipcregs_t *cc;
uint origidx;
uint32 clock;
@@ -1846,7 +1846,7 @@
static uint32 ilpcycles_per_sec = 0;
-uint32 BCMINITFN(si_pmu_ilp_clock) (si_t * sih, osl_t * osh) {
+uint32 BCMINITFN(si_pmu_ilp_clock) (si_t *sih, osl_t *osh) {
if (ISSIM_ENAB(sih))
return ILP_CLOCK;
@@ -1909,7 +1909,7 @@
#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
void
-BCMINITFN(si_sdiod_drive_strength_init) (si_t * sih, osl_t * osh,
+BCMINITFN(si_sdiod_drive_strength_init) (si_t *sih, osl_t *osh,
uint32 drivestrength) {
chipcregs_t *cc;
uint origidx, intr_val = 0;
@@ -1969,7 +1969,7 @@
}
/* initialize PMU */
-void BCMATTACHFN(si_pmu_init) (si_t * sih, osl_t * osh) {
+void BCMATTACHFN(si_pmu_init) (si_t *sih, osl_t *osh) {
chipcregs_t *cc;
uint origidx;
@@ -2000,7 +2000,7 @@
/* Return up time in ILP cycles for the given resource. */
static uint
-BCMINITFN(si_pmu_res_uptime) (si_t * sih, osl_t * osh, chipcregs_t * cc,
+BCMINITFN(si_pmu_res_uptime) (si_t *sih, osl_t *osh, chipcregs_t *cc,
uint8 rsrc) {
uint32 deps;
uint up, i, dup, dmax;
@@ -2037,7 +2037,7 @@
/* Return dependancies (direct or all/indirect) for the given resources */
static uint32
-si_pmu_res_deps(si_t * sih, osl_t * osh, chipcregs_t * cc, uint32 rsrcs,
+si_pmu_res_deps(si_t *sih, osl_t *osh, chipcregs_t *cc, uint32 rsrcs,
bool all)
{
uint32 deps = 0;
@@ -2057,7 +2057,7 @@
}
/* power up/down OTP through PMU resources */
-void si_pmu_otp_power(si_t * sih, osl_t * osh, bool on)
+void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on)
{
chipcregs_t *cc;
uint origidx;
@@ -2127,7 +2127,7 @@
si_setcoreidx(sih, origidx);
}
-void si_pmu_rcal(si_t * sih, osl_t * osh)
+void si_pmu_rcal(si_t *sih, osl_t *osh)
{
chipcregs_t *cc;
uint origidx;
@@ -2210,7 +2210,7 @@
si_setcoreidx(sih, origidx);
}
-void si_pmu_spuravoid(si_t * sih, osl_t * osh, uint8 spuravoid)
+void si_pmu_spuravoid(si_t *sih, osl_t *osh, uint8 spuravoid)
{
chipcregs_t *cc;
uint origidx, intr_val;
@@ -2247,7 +2247,7 @@
}
static void
-si_pmu_spuravoid_pllupdate(si_t * sih, chipcregs_t * cc, osl_t * osh,
+si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, osl_t *osh,
uint8 spuravoid)
{
uint32 tmp = 0;
@@ -2443,7 +2443,7 @@
W_REG(osh, &cc->pmucontrol, tmp);
}
-bool si_pmu_is_otp_powered(si_t * sih, osl_t * osh)
+bool si_pmu_is_otp_powered(si_t *sih, osl_t *osh)
{
uint idx;
chipcregs_t *cc;
@@ -2495,9 +2495,9 @@
void
#if defined(BCMDBG)
-si_pmu_sprom_enable(si_t * sih, osl_t * osh, bool enable)
+si_pmu_sprom_enable(si_t *sih, osl_t *osh, bool enable)
#else
-BCMATTACHFN(si_pmu_sprom_enable) (si_t * sih, osl_t * osh, bool enable)
+BCMATTACHFN(si_pmu_sprom_enable) (si_t *sih, osl_t *osh, bool enable)
#endif
{
chipcregs_t *cc;
@@ -2513,7 +2513,7 @@
}
/* initialize PMU chip controls and other chip level stuff */
-void BCMATTACHFN(si_pmu_chip_init) (si_t * sih, osl_t * osh) {
+void BCMATTACHFN(si_pmu_chip_init) (si_t *sih, osl_t *osh) {
uint origidx;
ASSERT(sih->cccaps & CC_CAP_PMU);
@@ -2534,7 +2534,7 @@
}
/* initialize PMU switch/regulators */
-void BCMATTACHFN(si_pmu_swreg_init) (si_t * sih, osl_t * osh) {
+void BCMATTACHFN(si_pmu_swreg_init) (si_t *sih, osl_t *osh) {
ASSERT(sih->cccaps & CC_CAP_PMU);
switch (CHIPID(sih->chip)) {
@@ -2559,7 +2559,7 @@
}
}
-void si_pmu_radio_enable(si_t * sih, bool enable)
+void si_pmu_radio_enable(si_t *sih, bool enable)
{
ASSERT(sih->cccaps & CC_CAP_PMU);
@@ -2577,7 +2577,7 @@
/* Wait for a particular clock level to be on the backplane */
uint32
-si_pmu_waitforclk_on_backplane(si_t * sih, osl_t * osh, uint32 clk,
+si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh, uint32 clk,
uint32 delay)
{
chipcregs_t *cc;
@@ -2606,7 +2606,7 @@
#define EXT_ILP_HZ 32768
-uint32 BCMATTACHFN(si_pmu_measure_alpclk) (si_t * sih, osl_t * osh) {
+uint32 BCMATTACHFN(si_pmu_measure_alpclk) (si_t *sih, osl_t *osh) {
chipcregs_t *cc;
uint origidx;
uint32 alp_khz;
@@ -2653,7 +2653,7 @@
return alp_khz;
}
-static void BCMATTACHFN(si_pmu_set_4330_plldivs) (si_t * sih) {
+static void BCMATTACHFN(si_pmu_set_4330_plldivs) (si_t *sih) {
uint32 FVCO = si_pmu1_pllfvco0(sih) / 1000;
uint32 m1div, m2div, m3div, m4div, m5div, m6div;
uint32 pllc1, pllc2;
diff --git a/drivers/staging/brcm80211/util/linux_osl.c b/drivers/staging/brcm80211/util/linux_osl.c
index a1898bb..725f90d 100644
--- a/drivers/staging/brcm80211/util/linux_osl.c
+++ b/drivers/staging/brcm80211/util/linux_osl.c
@@ -166,7 +166,7 @@
return osh;
}
-void osl_detach(osl_t * osh)
+void osl_detach(osl_t *osh)
{
if (osh == NULL)
return;
@@ -176,7 +176,7 @@
}
/* Return a new packet. zero out pkttag */
-void *BCMFASTPATH osl_pktget(osl_t * osh, uint len)
+void *BCMFASTPATH osl_pktget(osl_t *osh, uint len)
{
struct sk_buff *skb;
@@ -191,7 +191,7 @@
}
/* Free the driver packet. Free the tag if present */
-void BCMFASTPATH osl_pktfree(osl_t * osh, void *p, bool send)
+void BCMFASTPATH osl_pktfree(osl_t *osh, void *p, bool send)
{
struct sk_buff *skb, *nskb;
int nest = 0;
@@ -224,7 +224,7 @@
}
}
-uint32 osl_pci_read_config(osl_t * osh, uint offset, uint size)
+uint32 osl_pci_read_config(osl_t *osh, uint offset, uint size)
{
uint val = 0;
uint retry = PCI_CFG_RETRY;
@@ -249,7 +249,7 @@
return (val);
}
-void osl_pci_write_config(osl_t * osh, uint offset, uint size, uint val)
+void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
{
uint retry = PCI_CFG_RETRY;
@@ -274,7 +274,7 @@
}
/* return bus # for the pci device pointed by osh->pdev */
-uint osl_pci_bus(osl_t * osh)
+uint osl_pci_bus(osl_t *osh)
{
ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
@@ -282,7 +282,7 @@
}
/* return slot # for the pci device pointed by osh->pdev */
-uint osl_pci_slot(osl_t * osh)
+uint osl_pci_slot(osl_t *osh)
{
ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
@@ -290,21 +290,21 @@
}
static void
-osl_pcmcia_attr(osl_t * osh, uint offset, char *buf, int size, bool write)
+osl_pcmcia_attr(osl_t *osh, uint offset, char *buf, int size, bool write)
{
}
-void osl_pcmcia_read_attr(osl_t * osh, uint offset, void *buf, int size)
+void osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size)
{
osl_pcmcia_attr(osh, offset, (char *)buf, size, FALSE);
}
-void osl_pcmcia_write_attr(osl_t * osh, uint offset, void *buf, int size)
+void osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size)
{
osl_pcmcia_attr(osh, offset, (char *)buf, size, TRUE);
}
-void *osl_malloc(osl_t * osh, uint size)
+void *osl_malloc(osl_t *osh, uint size)
{
void *addr;
@@ -323,7 +323,7 @@
return (addr);
}
-void osl_mfree(osl_t * osh, void *addr, uint size)
+void osl_mfree(osl_t *osh, void *addr, uint size)
{
if (osh) {
ASSERT(osh->magic == OS_HANDLE_MAGIC);
@@ -332,13 +332,13 @@
kfree(addr);
}
-uint osl_malloced(osl_t * osh)
+uint osl_malloced(osl_t *osh)
{
ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
return (osh->malloced);
}
-uint osl_malloc_failed(osl_t * osh)
+uint osl_malloc_failed(osl_t *osh)
{
ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
return (osh->failed);
@@ -349,8 +349,8 @@
return (PAGE_SIZE);
}
-void *osl_dma_alloc_consistent(osl_t * osh, uint size, uint16 align_bits,
- uint * alloced, ulong * pap)
+void *osl_dma_alloc_consistent(osl_t *osh, uint size, uint16 align_bits,
+ uint *alloced, ulong *pap)
{
uint16 align = (1 << align_bits);
ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
@@ -362,14 +362,14 @@
return (pci_alloc_consistent(osh->pdev, size, (dma_addr_t *) pap));
}
-void osl_dma_free_consistent(osl_t * osh, void *va, uint size, ulong pa)
+void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa)
{
ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
pci_free_consistent(osh->pdev, size, va, (dma_addr_t) pa);
}
-uint BCMFASTPATH osl_dma_map(osl_t * osh, void *va, uint size, int direction)
+uint BCMFASTPATH osl_dma_map(osl_t *osh, void *va, uint size, int direction)
{
int dir;
@@ -378,7 +378,7 @@
return (pci_map_single(osh->pdev, va, size, dir));
}
-void BCMFASTPATH osl_dma_unmap(osl_t * osh, uint pa, uint size, int direction)
+void BCMFASTPATH osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction)
{
int dir;
@@ -448,7 +448,7 @@
/* Clone a packet.
* The pkttag contents are NOT cloned.
*/
-void *osl_pktdup(osl_t * osh, void *skb)
+void *osl_pktdup(osl_t *osh, void *skb)
{
void *p;
@@ -465,7 +465,7 @@
}
#ifdef BCMSDIO
-uint8 osl_readb(osl_t * osh, volatile uint8 * r)
+uint8 osl_readb(osl_t *osh, volatile uint8 *r)
{
osl_rreg_fn_t rreg = ((osl_pubinfo_t *) osh)->rreg_fn;
void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx;
@@ -473,7 +473,7 @@
return (uint8) ((rreg) (ctx, (void *)r, sizeof(uint8)));
}
-uint16 osl_readw(osl_t * osh, volatile uint16 * r)
+uint16 osl_readw(osl_t *osh, volatile uint16 *r)
{
osl_rreg_fn_t rreg = ((osl_pubinfo_t *) osh)->rreg_fn;
void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx;
@@ -481,7 +481,7 @@
return (uint16) ((rreg) (ctx, (void *)r, sizeof(uint16)));
}
-uint32 osl_readl(osl_t * osh, volatile uint32 * r)
+uint32 osl_readl(osl_t *osh, volatile uint32 *r)
{
osl_rreg_fn_t rreg = ((osl_pubinfo_t *) osh)->rreg_fn;
void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx;
@@ -489,7 +489,7 @@
return (uint32) ((rreg) (ctx, (void *)r, sizeof(uint32)));
}
-void osl_writeb(osl_t * osh, volatile uint8 * r, uint8 v)
+void osl_writeb(osl_t *osh, volatile uint8 *r, uint8 v)
{
osl_wreg_fn_t wreg = ((osl_pubinfo_t *) osh)->wreg_fn;
void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx;
@@ -497,7 +497,7 @@
((wreg) (ctx, (void *)r, v, sizeof(uint8)));
}
-void osl_writew(osl_t * osh, volatile uint16 * r, uint16 v)
+void osl_writew(osl_t *osh, volatile uint16 *r, uint16 v)
{
osl_wreg_fn_t wreg = ((osl_pubinfo_t *) osh)->wreg_fn;
void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx;
@@ -505,7 +505,7 @@
((wreg) (ctx, (void *)r, v, sizeof(uint16)));
}
-void osl_writel(osl_t * osh, volatile uint32 * r, uint32 v)
+void osl_writel(osl_t *osh, volatile uint32 *r, uint32 v)
{
osl_wreg_fn_t wreg = ((osl_pubinfo_t *) osh)->wreg_fn;
void *ctx = ((osl_pubinfo_t *) osh)->reg_ctx;
diff --git a/drivers/staging/brcm80211/util/nicpci.c b/drivers/staging/brcm80211/util/nicpci.c
index feaa54f..4b828ab8 100644
--- a/drivers/staging/brcm80211/util/nicpci.c
+++ b/drivers/staging/brcm80211/util/nicpci.c
@@ -49,24 +49,24 @@
#define PCIE_PUB(sih) ((BUSTYPE((sih)->bustype) == PCI_BUS) && ((sih)->buscoretype == PCIE_CORE_ID))
/* routines to access mdio slave device registers */
-static bool pcie_mdiosetblock(pcicore_info_t * pi, uint blk);
-static int pcie_mdioop(pcicore_info_t * pi, uint physmedia, uint regaddr,
- bool write, uint * val);
-static int pcie_mdiowrite(pcicore_info_t * pi, uint physmedia, uint readdr,
+static bool pcie_mdiosetblock(pcicore_info_t *pi, uint blk);
+static int pcie_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr,
+ bool write, uint *val);
+static int pcie_mdiowrite(pcicore_info_t *pi, uint physmedia, uint readdr,
uint val);
-static int pcie_mdioread(pcicore_info_t * pi, uint physmedia, uint readdr,
- uint * ret_val);
+static int pcie_mdioread(pcicore_info_t *pi, uint physmedia, uint readdr,
+ uint *ret_val);
-static void pcie_extendL1timer(pcicore_info_t * pi, bool extend);
-static void pcie_clkreq_upd(pcicore_info_t * pi, uint state);
+static void pcie_extendL1timer(pcicore_info_t *pi, bool extend);
+static void pcie_clkreq_upd(pcicore_info_t *pi, uint state);
-static void pcie_war_aspm_clkreq(pcicore_info_t * pi);
-static void pcie_war_serdes(pcicore_info_t * pi);
-static void pcie_war_noplldown(pcicore_info_t * pi);
-static void pcie_war_polarity(pcicore_info_t * pi);
-static void pcie_war_pci_setup(pcicore_info_t * pi);
+static void pcie_war_aspm_clkreq(pcicore_info_t *pi);
+static void pcie_war_serdes(pcicore_info_t *pi);
+static void pcie_war_noplldown(pcicore_info_t *pi);
+static void pcie_war_polarity(pcicore_info_t *pi);
+static void pcie_war_pci_setup(pcicore_info_t *pi);
-static bool pcicore_pmecap(pcicore_info_t * pi);
+static bool pcicore_pmecap(pcicore_info_t *pi);
#define PCIE_ASPM(sih) ((PCIE_PUB(sih)) && (((sih)->buscorerev >= 3) && ((sih)->buscorerev <= 5)))
@@ -106,7 +106,7 @@
/* Initialize the PCI core. It's caller's responsibility to make sure that this is done
* only once
*/
-void *pcicore_init(si_t * sih, osl_t * osh, void *regs)
+void *pcicore_init(si_t *sih, osl_t *osh, void *regs)
{
pcicore_info_t *pi;
@@ -150,8 +150,8 @@
/* return cap_offset if requested capability exists in the PCI config space */
/* Note that it's caller's responsibility to make sure it's a pci bus */
uint8
-pcicore_find_pci_capability(osl_t * osh, uint8 req_cap_id, uchar * buf,
- uint32 * buflen)
+pcicore_find_pci_capability(osl_t *osh, uint8 req_cap_id, uchar *buf,
+ uint32 *buflen)
{
uint8 cap_id;
uint8 cap_ptr = 0;
@@ -211,7 +211,7 @@
/* ***** Register Access API */
uint
-pcie_readreg(osl_t * osh, sbpcieregs_t * pcieregs, uint addrtype, uint offset)
+pcie_readreg(osl_t *osh, sbpcieregs_t *pcieregs, uint addrtype, uint offset)
{
uint retval = 0xFFFFFFFF;
@@ -237,7 +237,7 @@
}
uint
-pcie_writereg(osl_t * osh, sbpcieregs_t * pcieregs, uint addrtype, uint offset,
+pcie_writereg(osl_t *osh, sbpcieregs_t *pcieregs, uint addrtype, uint offset,
uint val)
{
ASSERT(pcieregs != NULL);
@@ -258,7 +258,7 @@
return 0;
}
-static bool pcie_mdiosetblock(pcicore_info_t * pi, uint blk)
+static bool pcie_mdiosetblock(pcicore_info_t *pi, uint blk)
{
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
uint mdiodata, i = 0;
@@ -291,8 +291,8 @@
}
static int
-pcie_mdioop(pcicore_info_t * pi, uint physmedia, uint regaddr, bool write,
- uint * val)
+pcie_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, bool write,
+ uint *val)
{
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
uint mdiodata;
@@ -351,14 +351,14 @@
/* use the mdio interface to read from mdio slaves */
static int
-pcie_mdioread(pcicore_info_t * pi, uint physmedia, uint regaddr, uint * regval)
+pcie_mdioread(pcicore_info_t *pi, uint physmedia, uint regaddr, uint *regval)
{
return pcie_mdioop(pi, physmedia, regaddr, FALSE, regval);
}
/* use the mdio interface to write to mdio slaves */
static int
-pcie_mdiowrite(pcicore_info_t * pi, uint physmedia, uint regaddr, uint val)
+pcie_mdiowrite(pcicore_info_t *pi, uint physmedia, uint regaddr, uint val)
{
return pcie_mdioop(pi, physmedia, regaddr, TRUE, &val);
}
@@ -390,7 +390,7 @@
return 0;
}
-static void pcie_extendL1timer(pcicore_info_t * pi, bool extend)
+static void pcie_extendL1timer(pcicore_info_t *pi, bool extend)
{
uint32 w;
si_t *sih = pi->sih;
@@ -410,7 +410,7 @@
}
/* centralized clkreq control policy */
-static void pcie_clkreq_upd(pcicore_info_t * pi, uint state)
+static void pcie_clkreq_upd(pcicore_info_t *pi, uint state)
{
si_t *sih = pi->sih;
ASSERT(PCIE_PUB(sih));
@@ -452,7 +452,7 @@
/* ***** PCI core WARs ***** */
/* Done only once at attach time */
-static void pcie_war_polarity(pcicore_info_t * pi)
+static void pcie_war_polarity(pcicore_info_t *pi)
{
uint32 w;
@@ -477,7 +477,7 @@
* : Coming out of 'standby'/'hibernate'
* : If pcie_war_aspm_ovr state changed
*/
-static void pcie_war_aspm_clkreq(pcicore_info_t * pi)
+static void pcie_war_aspm_clkreq(pcicore_info_t *pi)
{
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
si_t *sih = pi->sih;
@@ -525,7 +525,7 @@
/* Apply the polarity determined at the start */
/* Needs to happen when coming out of 'standby'/'hibernate' */
-static void pcie_war_serdes(pcicore_info_t * pi)
+static void pcie_war_serdes(pcicore_info_t *pi)
{
uint32 w = 0;
@@ -542,7 +542,7 @@
/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
/* Needs to happen when coming out of 'standby'/'hibernate' */
-static void BCMINITFN(pcie_misc_config_fixup) (pcicore_info_t * pi) {
+static void BCMINITFN(pcie_misc_config_fixup) (pcicore_info_t *pi) {
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
uint16 val16, *reg16;
@@ -557,7 +557,7 @@
/* quick hack for testing */
/* Needs to happen when coming out of 'standby'/'hibernate' */
-static void pcie_war_noplldown(pcicore_info_t * pi)
+static void pcie_war_noplldown(pcicore_info_t *pi)
{
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
uint16 *reg16;
@@ -574,7 +574,7 @@
}
/* Needs to happen when coming out of 'standby'/'hibernate' */
-static void pcie_war_pci_setup(pcicore_info_t * pi)
+static void pcie_war_pci_setup(pcicore_info_t *pi)
{
si_t *sih = pi->sih;
osl_t *osh = pi->osh;
@@ -717,7 +717,7 @@
/* ***** Wake-on-wireless-LAN (WOWL) support functions ***** */
/* Just uses PCI config accesses to find out, when needed before sb_attach is done */
-bool pcicore_pmecap_fast(osl_t * osh)
+bool pcicore_pmecap_fast(osl_t *osh)
{
uint8 cap_ptr;
uint32 pmecap;
@@ -737,7 +737,7 @@
/* return TRUE if PM capability exists in the pci config space
* Uses and caches the information using core handle
*/
-static bool pcicore_pmecap(pcicore_info_t * pi)
+static bool pcicore_pmecap(pcicore_info_t *pi)
{
uint8 cap_ptr;
uint32 pmecap;
diff --git a/drivers/staging/brcm80211/util/nvram/nvram_ro.c b/drivers/staging/brcm80211/util/nvram/nvram_ro.c
index 68c69ee..4e538ac 100644
--- a/drivers/staging/brcm80211/util/nvram/nvram_ro.c
+++ b/drivers/staging/brcm80211/util/nvram/nvram_ro.c
@@ -46,7 +46,7 @@
#if defined(FLASH)
/* copy flash to ram */
-static void BCMINITFN(get_flash_nvram) (si_t * sih, struct nvram_header * nvh) {
+static void BCMINITFN(get_flash_nvram) (si_t *sih, struct nvram_header *nvh) {
osl_t *osh;
uint nvs, bufsz;
vars_t *new;
diff --git a/drivers/staging/brcm80211/util/qmath.c b/drivers/staging/brcm80211/util/qmath.c
index 99a1776..17844b3 100644
--- a/drivers/staging/brcm80211/util/qmath.c
+++ b/drivers/staging/brcm80211/util/qmath.c
@@ -337,7 +337,7 @@
to this function. The qformat of quotient is adjusted appropriately such that
the quotient occupies all 16 bits.
*/
-int16 qm_div16(int16 num, int16 denom, int16 * qQuotient)
+int16 qm_div16(int16 num, int16 denom, int16 *qQuotient)
{
int16 sign;
int16 nNum, nDenom;
@@ -380,7 +380,7 @@
to this function. The qformat of quotient is adjusted appropriately such that
the quotient occupies all 16 bits.
*/
-int16 qm_div163232(int32 num, int32 denom, int16 * qquotient)
+int16 qm_div163232(int32 num, int32 denom, int16 *qquotient)
{
int32 sign;
int16 nNum, nDenom;
@@ -545,7 +545,7 @@
Note/Problem:
For accurate results input should be in normalized or near normalized form.
*/
-void qm_log10(int32 N, int16 qN, int16 * log10N, int16 * qLog10N)
+void qm_log10(int32 N, int16 qN, int16 *log10N, int16 *qLog10N)
{
int16 s16norm, s16tableIndex, s16errorApproximation;
uint16 u16offset;
@@ -631,7 +631,7 @@
qsqrtN - address where q format of 1/N has to be written.
*/
#define qx 29
-void qm_1byN(int32 N, int16 qN, int32 * result, int16 * qResult)
+void qm_1byN(int32 N, int16 qN, int32 *result, int16 *qResult)
{
int16 normN;
int32 s32firstTerm, s32secondTerm, x;
diff --git a/drivers/staging/brcm80211/util/siutils.c b/drivers/staging/brcm80211/util/siutils.c
index af35564..aa39893 100644
--- a/drivers/staging/brcm80211/util/siutils.c
+++ b/drivers/staging/brcm80211/util/siutils.c
@@ -52,20 +52,20 @@
#endif
/* local prototypes */
-static si_info_t *si_doattach(si_info_t * sii, uint devid, osl_t * osh,
+static si_info_t *si_doattach(si_info_t *sii, uint devid, osl_t *osh,
void *regs, uint bustype, void *sdh, char **vars,
- uint * varsz);
-static bool si_buscore_prep(si_info_t * sii, uint bustype, uint devid,
+ uint *varsz);
+static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid,
void *sdh);
-static bool si_buscore_setup(si_info_t * sii, chipcregs_t * cc, uint bustype,
- uint32 savewin, uint * origidx, void *regs);
-static void si_nvram_process(si_info_t * sii, char *pvars);
+static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,
+ uint32 savewin, uint *origidx, void *regs);
+static void si_nvram_process(si_info_t *sii, char *pvars);
/* dev path concatenation util */
-static char *si_devpathvar(si_t * sih, char *var, int len, const char *name);
-static bool _si_clkctl_cc(si_info_t * sii, uint mode);
-static bool si_ispcie(si_info_t * sii);
-static uint BCMINITFN(socram_banksize) (si_info_t * sii, sbsocramregs_t * r,
+static char *si_devpathvar(si_t *sih, char *var, int len, const char *name);
+static bool _si_clkctl_cc(si_info_t *sii, uint mode);
+static bool si_ispcie(si_info_t *sii);
+static uint BCMINITFN(socram_banksize) (si_info_t *sii, sbsocramregs_t *r,
uint8 idx, uint8 mtype);
/* global variable to indicate reservation/release of gpio's */
@@ -82,9 +82,9 @@
* vars - pointer to a pointer area for "environment" variables
* varsz - pointer to int to return the size of the vars
*/
-si_t *BCMATTACHFN(si_attach) (uint devid, osl_t * osh, void *regs,
+si_t *BCMATTACHFN(si_attach) (uint devid, osl_t *osh, void *regs,
uint bustype, void *sdh, char **vars,
- uint * varsz) {
+ uint *varsz) {
si_info_t *sii;
/* alloc si_info_t */
@@ -111,7 +111,7 @@
static uint32 wd_msticks; /* watchdog timer ticks normalized to ms */
static bool
-BCMATTACHFN(si_buscore_prep) (si_info_t * sii, uint bustype, uint devid,
+BCMATTACHFN(si_buscore_prep) (si_info_t *sii, uint bustype, uint devid,
void *sdh) {
/* kludge to enable the clock on the 4306 which lacks a slowclock */
@@ -165,8 +165,8 @@
}
static bool
-BCMATTACHFN(si_buscore_setup) (si_info_t * sii, chipcregs_t * cc, uint bustype,
- uint32 savewin, uint * origidx, void *regs) {
+BCMATTACHFN(si_buscore_setup) (si_info_t *sii, chipcregs_t *cc, uint bustype,
+ uint32 savewin, uint *origidx, void *regs) {
bool pci, pcie;
uint i;
uint pciidx, pcieidx, pcirev, pcierev;
@@ -290,7 +290,7 @@
return TRUE;
}
-static void BCMATTACHFN(si_nvram_process) (si_info_t * sii, char *pvars) {
+static void BCMATTACHFN(si_nvram_process) (si_info_t *sii, char *pvars) {
uint w = 0;
/* get boardtype and boardrev */
@@ -349,10 +349,10 @@
/* this is will make Sonics calls directly, since Sonics is no longer supported in the Si abstraction */
/* this has been customized for the bcm 4329 ONLY */
#ifdef BCMSDIO
-static si_info_t *BCMATTACHFN(si_doattach) (si_info_t * sii, uint devid,
- osl_t * osh, void *regs,
+static si_info_t *BCMATTACHFN(si_doattach) (si_info_t *sii, uint devid,
+ osl_t *osh, void *regs,
uint bustype, void *sdh,
- char **vars, uint * varsz) {
+ char **vars, uint *varsz) {
struct si_pub *sih = &sii->pub;
uint32 w, savewin;
chipcregs_t *cc;
@@ -471,10 +471,10 @@
}
#else /* BCMSDIO */
-static si_info_t *BCMATTACHFN(si_doattach) (si_info_t * sii, uint devid,
- osl_t * osh, void *regs,
+static si_info_t *BCMATTACHFN(si_doattach) (si_info_t *sii, uint devid,
+ osl_t *osh, void *regs,
uint bustype, void *sdh,
- char **vars, uint * varsz) {
+ char **vars, uint *varsz) {
struct si_pub *sih = &sii->pub;
uint32 w, savewin;
chipcregs_t *cc;
@@ -666,7 +666,7 @@
#endif /* BCMSDIO */
/* may be called with core in reset */
-void BCMATTACHFN(si_detach) (si_t * sih) {
+void BCMATTACHFN(si_detach) (si_t *sih) {
si_info_t *sii;
uint idx;
@@ -698,7 +698,7 @@
MFREE(sii->osh, sii, sizeof(si_info_t));
}
-void *si_osh(si_t * sih)
+void *si_osh(si_t *sih)
{
si_info_t *sii;
@@ -706,7 +706,7 @@
return sii->osh;
}
-void si_setosh(si_t * sih, osl_t * osh)
+void si_setosh(si_t *sih, osl_t *osh)
{
si_info_t *sii;
@@ -720,7 +720,7 @@
/* register driver interrupt disabling and restoring callback functions */
void
-si_register_intr_callback(si_t * sih, void *intrsoff_fn, void *intrsrestore_fn,
+si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
void *intrsenabled_fn, void *intr_arg)
{
si_info_t *sii;
@@ -736,7 +736,7 @@
sii->dev_coreid = sii->coreid[sii->curidx];
}
-void si_deregister_intr_callback(si_t * sih)
+void si_deregister_intr_callback(si_t *sih)
{
si_info_t *sii;
@@ -744,7 +744,7 @@
sii->intrsoff_fn = NULL;
}
-uint si_intflag(si_t * sih)
+uint si_intflag(si_t *sih)
{
si_info_t *sii = SI_INFO(sih);
@@ -758,7 +758,7 @@
}
}
-uint si_flag(si_t * sih)
+uint si_flag(si_t *sih)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
return ai_flag(sih);
@@ -768,7 +768,7 @@
}
}
-void si_setint(si_t * sih, int siflag)
+void si_setint(si_t *sih, int siflag)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
ai_setint(sih, siflag);
@@ -777,7 +777,7 @@
}
#ifndef BCMSDIO
-uint si_coreid(si_t * sih)
+uint si_coreid(si_t *sih)
{
si_info_t *sii;
@@ -786,7 +786,7 @@
}
#endif
-uint si_coreidx(si_t * sih)
+uint si_coreidx(si_t *sih)
{
si_info_t *sii;
@@ -795,7 +795,7 @@
}
/* return the core-type instantiation # of the current core */
-uint si_coreunit(si_t * sih)
+uint si_coreunit(si_t *sih)
{
si_info_t *sii;
uint idx;
@@ -819,7 +819,7 @@
return (coreunit);
}
-uint si_corevendor(si_t * sih)
+uint si_corevendor(si_t *sih)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
return ai_corevendor(sih);
@@ -829,13 +829,13 @@
}
}
-bool si_backplane64(si_t * sih)
+bool si_backplane64(si_t *sih)
{
return ((sih->cccaps & CC_CAP_BKPLN64) != 0);
}
#ifndef BCMSDIO
-uint si_corerev(si_t * sih)
+uint si_corerev(si_t *sih)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
return ai_corerev(sih);
@@ -847,7 +847,7 @@
#endif
/* return index of coreid or BADIDX if not found */
-uint si_findcoreidx(si_t * sih, uint coreid, uint coreunit)
+uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit)
{
si_info_t *sii;
uint found;
@@ -868,7 +868,7 @@
}
/* return list of found cores */
-uint si_corelist(si_t * sih, uint coreid[])
+uint si_corelist(si_t *sih, uint coreid[])
{
si_info_t *sii;
@@ -880,7 +880,7 @@
}
/* return current register mapping */
-void *si_coreregs(si_t * sih)
+void *si_coreregs(si_t *sih)
{
si_info_t *sii;
@@ -895,7 +895,7 @@
* must be called with interrupts off.
* Moreover, callers should keep interrupts off during switching out of and back to d11 core
*/
-void *si_setcore(si_t * sih, uint coreid, uint coreunit)
+void *si_setcore(si_t *sih, uint coreid, uint coreunit)
{
uint idx;
@@ -916,7 +916,7 @@
}
#ifndef BCMSDIO
-void *si_setcoreidx(si_t * sih, uint coreidx)
+void *si_setcoreidx(si_t *sih, uint coreidx)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
return ai_setcoreidx(sih, coreidx);
@@ -928,7 +928,7 @@
#endif
/* Turn off interrupt as required by sb_setcore, before switch core */
-void *si_switch_core(si_t * sih, uint coreid, uint * origidx, uint * intr_val)
+void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val)
{
void *cc;
si_info_t *sii;
@@ -955,7 +955,7 @@
}
/* restore coreidx and restore interrupt */
-void si_restore_core(si_t * sih, uint coreid, uint intr_val)
+void si_restore_core(si_t *sih, uint coreid, uint intr_val)
{
si_info_t *sii;
@@ -968,7 +968,7 @@
INTR_RESTORE(sii, intr_val);
}
-int si_numaddrspaces(si_t * sih)
+int si_numaddrspaces(si_t *sih)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
return ai_numaddrspaces(sih);
@@ -978,7 +978,7 @@
}
}
-uint32 si_addrspace(si_t * sih, uint asidx)
+uint32 si_addrspace(si_t *sih, uint asidx)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
return ai_addrspace(sih, asidx);
@@ -988,7 +988,7 @@
}
}
-uint32 si_addrspacesize(si_t * sih, uint asidx)
+uint32 si_addrspacesize(si_t *sih, uint asidx)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
return ai_addrspacesize(sih, asidx);
@@ -998,7 +998,7 @@
}
}
-uint32 si_core_cflags(si_t * sih, uint32 mask, uint32 val)
+uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
return ai_core_cflags(sih, mask, val);
@@ -1008,7 +1008,7 @@
}
}
-void si_core_cflags_wo(si_t * sih, uint32 mask, uint32 val)
+void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
ai_core_cflags_wo(sih, mask, val);
@@ -1016,7 +1016,7 @@
ASSERT(0);
}
-uint32 si_core_sflags(si_t * sih, uint32 mask, uint32 val)
+uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
return ai_core_sflags(sih, mask, val);
@@ -1026,7 +1026,7 @@
}
}
-bool si_iscoreup(si_t * sih)
+bool si_iscoreup(si_t *sih)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
return ai_iscoreup(sih);
@@ -1040,7 +1040,7 @@
}
}
-void si_write_wrapperreg(si_t * sih, uint32 offset, uint32 val)
+void si_write_wrapperreg(si_t *sih, uint32 offset, uint32 val)
{
/* only for 4319, no requirement for SOCI_SB */
if (CHIPTYPE(sih->socitype) == SOCI_AI) {
@@ -1048,7 +1048,7 @@
}
}
-uint si_corereg(si_t * sih, uint coreidx, uint regoff, uint mask, uint val)
+uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
@@ -1063,7 +1063,7 @@
}
}
-void si_core_disable(si_t * sih, uint32 bits)
+void si_core_disable(si_t *sih, uint32 bits)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
@@ -1074,7 +1074,7 @@
#endif
}
-void si_core_reset(si_t * sih, uint32 bits, uint32 resetbits)
+void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
{
if (CHIPTYPE(sih->socitype) == SOCI_AI)
ai_core_reset(sih, bits, resetbits);
@@ -1085,7 +1085,7 @@
}
/* Run bist on current core. Caller needs to take care of core-specific bist hazards */
-int si_corebist(si_t * sih)
+int si_corebist(si_t *sih)
{
uint32 cflags;
int result = 0;
@@ -1212,7 +1212,7 @@
}
}
-uint32 BCMINITFN(si_clock) (si_t * sih) {
+uint32 BCMINITFN(si_clock) (si_t *sih) {
si_info_t *sii;
chipcregs_t *cc;
uint32 n, m;
@@ -1254,14 +1254,14 @@
return rate;
}
-uint32 BCMINITFN(si_alp_clock) (si_t * sih) {
+uint32 BCMINITFN(si_alp_clock) (si_t *sih) {
if (PMUCTL_ENAB(sih))
return si_pmu_alp_clock(sih, si_osh(sih));
return ALP_CLOCK;
}
-uint32 BCMINITFN(si_ilp_clock) (si_t * sih) {
+uint32 BCMINITFN(si_ilp_clock) (si_t *sih) {
if (PMUCTL_ENAB(sih))
return si_pmu_ilp_clock(sih, si_osh(sih));
@@ -1269,7 +1269,7 @@
}
/* set chip watchdog reset timer to fire in 'ticks' */
-void si_watchdog(si_t * sih, uint ticks)
+void si_watchdog(si_t *sih, uint ticks)
{
uint nb, maxt;
@@ -1313,12 +1313,12 @@
}
/* trigger watchdog reset after ms milliseconds */
-void si_watchdog_ms(si_t * sih, uint32 ms)
+void si_watchdog_ms(si_t *sih, uint32 ms)
{
si_watchdog(sih, wd_msticks * ms);
}
-uint16 BCMATTACHFN(si_d11_devid) (si_t * sih) {
+uint16 BCMATTACHFN(si_d11_devid) (si_t *sih) {
si_info_t *sii = SI_INFO(sih);
uint16 device;
@@ -1336,7 +1336,7 @@
}
/* return the slow clock source - LPO, XTAL, or PCI */
-static uint si_slowclk_src(si_info_t * sii)
+static uint si_slowclk_src(si_info_t *sii)
{
chipcregs_t *cc;
@@ -1357,7 +1357,7 @@
}
/* return the ILP (slowclock) min or max frequency */
-static uint si_slowclk_freq(si_info_t * sii, bool max_freq, chipcregs_t * cc)
+static uint si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
{
uint32 slowclk;
uint div;
@@ -1398,7 +1398,7 @@
return (0);
}
-static void BCMINITFN(si_clkctl_setdelay) (si_info_t * sii, void *chipcregs) {
+static void BCMINITFN(si_clkctl_setdelay) (si_info_t *sii, void *chipcregs) {
chipcregs_t *cc = (chipcregs_t *) chipcregs;
uint slowmaxfreq, pll_delay, slowclk;
uint pll_on_delay, fref_sel_delay;
@@ -1425,7 +1425,7 @@
}
/* initialize power control delay registers */
-void BCMINITFN(si_clkctl_init) (si_t * sih) {
+void BCMINITFN(si_clkctl_init) (si_t *sih) {
si_info_t *sii;
uint origidx = 0;
chipcregs_t *cc;
@@ -1457,7 +1457,7 @@
}
/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
-uint16 BCMINITFN(si_clkctl_fast_pwrup_delay) (si_t * sih) {
+uint16 BCMINITFN(si_clkctl_fast_pwrup_delay) (si_t *sih) {
si_info_t *sii;
uint origidx = 0;
chipcregs_t *cc;
@@ -1502,7 +1502,7 @@
}
/* turn primary xtal and/or pll off/on */
-int si_clkctl_xtal(si_t * sih, uint what, bool on)
+int si_clkctl_xtal(si_t *sih, uint what, bool on)
{
si_info_t *sii;
uint32 in, out, outen;
@@ -1587,7 +1587,7 @@
* this is a wrapper over the next internal function
* to allow flexible policy settings for outside caller
*/
-bool si_clkctl_cc(si_t * sih, uint mode)
+bool si_clkctl_cc(si_t *sih, uint mode)
{
si_info_t *sii;
@@ -1604,7 +1604,7 @@
}
/* clk control mechanism through chipcommon, no policy checking */
-static bool _si_clkctl_cc(si_info_t * sii, uint mode)
+static bool _si_clkctl_cc(si_info_t *sii, uint mode)
{
uint origidx = 0;
chipcregs_t *cc;
@@ -1692,7 +1692,7 @@
}
/* Build device path. Support SI, PCI, and JTAG for now. */
-int BCMATTACHFN(si_devpath) (si_t * sih, char *path, int size) {
+int BCMATTACHFN(si_devpath) (si_t *sih, char *path, int size) {
int slen;
ASSERT(path != NULL);
@@ -1734,7 +1734,7 @@
}
/* Get a variable, but only if it has a devpath prefix */
-char *BCMATTACHFN(si_getdevpathvar) (si_t * sih, const char *name) {
+char *BCMATTACHFN(si_getdevpathvar) (si_t *sih, const char *name) {
char varname[SI_DEVPATH_BUFSZ + 32];
si_devpathvar(sih, varname, sizeof(varname), name);
@@ -1743,7 +1743,7 @@
}
/* Get a variable, but only if it has a devpath prefix */
-int BCMATTACHFN(si_getdevpathintvar) (si_t * sih, const char *name) {
+int BCMATTACHFN(si_getdevpathintvar) (si_t *sih, const char *name) {
#if defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS)
return (getintvar(NULL, name));
#else
@@ -1755,7 +1755,7 @@
#endif
}
-char *si_getnvramflvar(si_t * sih, const char *name)
+char *si_getnvramflvar(si_t *sih, const char *name)
{
return (getvar(NULL, name));
}
@@ -1765,7 +1765,7 @@
* Nothing is done to the arguments if len == 0 or var is NULL, var is still returned.
* On overflow, the first char will be set to '\0'.
*/
-static char *BCMATTACHFN(si_devpathvar) (si_t * sih, char *var, int len,
+static char *BCMATTACHFN(si_devpathvar) (si_t *sih, char *var, int len,
const char *name) {
uint path_len;
@@ -1784,7 +1784,7 @@
return var;
}
-uint32 si_pciereg(si_t * sih, uint32 offset, uint32 mask, uint32 val, uint type)
+uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type)
{
si_info_t *sii;
@@ -1799,7 +1799,7 @@
}
uint32
-si_pcieserdesreg(si_t * sih, uint32 mdioslave, uint32 offset, uint32 mask,
+si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask,
uint32 val)
{
si_info_t *sii;
@@ -1816,7 +1816,7 @@
}
/* return TRUE if PCIE capability exists in the pci config space */
-static bool si_ispcie(si_info_t * sii)
+static bool si_ispcie(si_info_t *sii)
{
uint8 cap_ptr;
@@ -1834,7 +1834,7 @@
/* Wake-on-wireless-LAN (WOWL) support functions */
/* Enable PME generation and disable clkreq */
-void si_pci_pmeen(si_t * sih)
+void si_pci_pmeen(si_t *sih)
{
si_info_t *sii;
@@ -1844,7 +1844,7 @@
}
/* Return TRUE if PME status is set */
-bool si_pci_pmestat(si_t * sih)
+bool si_pci_pmestat(si_t *sih)
{
si_info_t *sii;
@@ -1854,7 +1854,7 @@
}
/* Disable PME generation, clear the PME status bit if set */
-void si_pci_pmeclr(si_t * sih)
+void si_pci_pmeclr(si_t *sih)
{
si_info_t *sii;
@@ -1865,7 +1865,7 @@
#ifdef BCMSDIO
/* initialize the sdio core */
-void si_sdio_init(si_t * sih)
+void si_sdio_init(si_t *sih)
{
si_info_t *sii = SI_INFO(sih);
@@ -1903,7 +1903,7 @@
}
#endif /* BCMSDIO */
-bool BCMATTACHFN(si_pci_war16165) (si_t * sih) {
+bool BCMATTACHFN(si_pci_war16165) (si_t *sih) {
si_info_t *sii;
sii = SI_INFO(sih);
@@ -1916,7 +1916,7 @@
* but are in systems that still want the benefits of ASPM
* Note that this should be done AFTER si_doattach
*/
-void si_pcie_war_ovr_update(si_t * sih, uint8 aspm)
+void si_pcie_war_ovr_update(si_t *sih, uint8 aspm)
{
si_info_t *sii;
@@ -1929,7 +1929,7 @@
}
/* back door for other module to override chippkg */
-void si_chippkg_set(si_t * sih, uint val)
+void si_chippkg_set(si_t *sih, uint val)
{
si_info_t *sii;
@@ -1938,7 +1938,7 @@
sii->pub.chippkg = val;
}
-void BCMINITFN(si_pci_up) (si_t * sih) {
+void BCMINITFN(si_pci_up) (si_t *sih) {
si_info_t *sii;
sii = SI_INFO(sih);
@@ -1956,7 +1956,7 @@
}
/* Unconfigure and/or apply various WARs when system is going to sleep mode */
-void BCMUNINITFN(si_pci_sleep) (si_t * sih) {
+void BCMUNINITFN(si_pci_sleep) (si_t *sih) {
si_info_t *sii;
sii = SI_INFO(sih);
@@ -1965,7 +1965,7 @@
}
/* Unconfigure and/or apply various WARs when going down */
-void BCMINITFN(si_pci_down) (si_t * sih) {
+void BCMINITFN(si_pci_down) (si_t *sih) {
si_info_t *sii;
sii = SI_INFO(sih);
@@ -1985,7 +1985,7 @@
* Configure the pci core for pci client (NIC) action
* coremask is the bitvec of cores by index to be enabled.
*/
-void BCMATTACHFN(si_pci_setup) (si_t * sih, uint coremask) {
+void BCMATTACHFN(si_pci_setup) (si_t *sih, uint coremask) {
si_info_t *sii;
sbpciregs_t *pciregs = NULL;
uint32 siflag = 0, w;
@@ -2042,7 +2042,7 @@
}
}
-uint8 si_pcieclkreq(si_t * sih, uint32 mask, uint32 val)
+uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val)
{
si_info_t *sii;
@@ -2053,7 +2053,7 @@
return pcie_clkreq(sii->pch, mask, val);
}
-uint32 si_pcielcreg(si_t * sih, uint32 mask, uint32 val)
+uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val)
{
si_info_t *sii;
@@ -2077,7 +2077,7 @@
* Fixup SROMless PCI device's configuration.
* The current core may be changed upon return.
*/
-int si_pci_fixcfg(si_t * sih)
+int si_pci_fixcfg(si_t *sih)
{
uint origidx, pciidx;
sbpciregs_t *pciregs = NULL;
@@ -2123,13 +2123,13 @@
}
/* change logical "focus" to the gpio core for optimized access */
-void *si_gpiosetcore(si_t * sih)
+void *si_gpiosetcore(si_t *sih)
{
return (si_setcoreidx(sih, SI_CC_IDX));
}
/* mask&set gpiocontrol bits */
-uint32 si_gpiocontrol(si_t * sih, uint32 mask, uint32 val, uint8 priority)
+uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority)
{
uint regoff;
@@ -2150,7 +2150,7 @@
}
/* mask&set gpio output enable bits */
-uint32 si_gpioouten(si_t * sih, uint32 mask, uint32 val, uint8 priority)
+uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority)
{
uint regoff;
@@ -2171,7 +2171,7 @@
}
/* mask&set gpio output bits */
-uint32 si_gpioout(si_t * sih, uint32 mask, uint32 val, uint8 priority)
+uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority)
{
uint regoff;
@@ -2192,7 +2192,7 @@
}
/* reserve one gpio */
-uint32 si_gpioreserve(si_t * sih, uint32 gpio_bitmask, uint8 priority)
+uint32 si_gpioreserve(si_t *sih, uint32 gpio_bitmask, uint8 priority)
{
si_info_t *sii;
@@ -2227,7 +2227,7 @@
* persists till some one overwrites it
*/
-uint32 si_gpiorelease(si_t * sih, uint32 gpio_bitmask, uint8 priority)
+uint32 si_gpiorelease(si_t *sih, uint32 gpio_bitmask, uint8 priority)
{
si_info_t *sii;
@@ -2258,7 +2258,7 @@
}
/* return the current gpioin register value */
-uint32 si_gpioin(si_t * sih)
+uint32 si_gpioin(si_t *sih)
{
si_info_t *sii;
uint regoff;
@@ -2271,7 +2271,7 @@
}
/* mask&set gpio interrupt polarity bits */
-uint32 si_gpiointpolarity(si_t * sih, uint32 mask, uint32 val, uint8 priority)
+uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority)
{
si_info_t *sii;
uint regoff;
@@ -2291,7 +2291,7 @@
}
/* mask&set gpio interrupt mask bits */
-uint32 si_gpiointmask(si_t * sih, uint32 mask, uint32 val, uint8 priority)
+uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority)
{
si_info_t *sii;
uint regoff;
@@ -2311,7 +2311,7 @@
}
/* assign the gpio to an led */
-uint32 si_gpioled(si_t * sih, uint32 mask, uint32 val)
+uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val)
{
si_info_t *sii;
@@ -2326,7 +2326,7 @@
}
/* mask&set gpio timer val */
-uint32 si_gpiotimerval(si_t * sih, uint32 mask, uint32 gpiotimerval)
+uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 gpiotimerval)
{
si_info_t *sii;
@@ -2340,7 +2340,7 @@
gpiotimerval));
}
-uint32 si_gpiopull(si_t * sih, bool updown, uint32 mask, uint32 val)
+uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val)
{
si_info_t *sii;
uint offs;
@@ -2355,7 +2355,7 @@
return (si_corereg(sih, SI_CC_IDX, offs, mask, val));
}
-uint32 si_gpioevent(si_t * sih, uint regtype, uint32 mask, uint32 val)
+uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val)
{
si_info_t *sii;
uint offs;
@@ -2376,7 +2376,7 @@
return (si_corereg(sih, SI_CC_IDX, offs, mask, val));
}
-void *BCMATTACHFN(si_gpio_handler_register) (si_t * sih, uint32 event,
+void *BCMATTACHFN(si_gpio_handler_register) (si_t *sih, uint32 event,
bool level, gpio_handler_t cb,
void *arg) {
si_info_t *sii;
@@ -2404,7 +2404,7 @@
return (void *)(gi);
}
-void BCMATTACHFN(si_gpio_handler_unregister) (si_t * sih, void *gpioh) {
+void BCMATTACHFN(si_gpio_handler_unregister) (si_t *sih, void *gpioh) {
si_info_t *sii;
gpioh_item_t *p, *n;
@@ -2434,7 +2434,7 @@
ASSERT(0); /* Not found in list */
}
-void si_gpio_handler_process(si_t * sih)
+void si_gpio_handler_process(si_t *sih)
{
si_info_t *sii;
gpioh_item_t *h;
@@ -2455,7 +2455,7 @@
si_gpioevent(sih, GPIO_REGEVT, edge, edge); /* clear edge-trigger status */
}
-uint32 si_gpio_int_enable(si_t * sih, bool enable)
+uint32 si_gpio_int_enable(si_t *sih, bool enable)
{
si_info_t *sii;
uint offs;
@@ -2471,7 +2471,7 @@
/* Return the size of the specified SOCRAM bank */
static uint
-socram_banksize(si_info_t * sii, sbsocramregs_t * regs, uint8 index,
+socram_banksize(si_info_t *sii, sbsocramregs_t *regs, uint8 index,
uint8 mem_type)
{
uint banksize, bankinfo;
@@ -2486,7 +2486,7 @@
return banksize;
}
-void si_socdevram(si_t * sih, bool set, uint8 * enable, uint8 * protect)
+void si_socdevram(si_t *sih, bool set, uint8 *enable, uint8 *protect)
{
si_info_t *sii;
uint origidx;
@@ -2561,7 +2561,7 @@
INTR_RESTORE(sii, intr_val);
}
-bool si_socdevram_pkg(si_t * sih)
+bool si_socdevram_pkg(si_t *sih)
{
if (si_socdevram_size(sih) > 0)
return TRUE;
@@ -2569,7 +2569,7 @@
return FALSE;
}
-uint32 si_socdevram_size(si_t * sih)
+uint32 si_socdevram_size(si_t *sih)
{
si_info_t *sii;
uint origidx;
@@ -2620,7 +2620,7 @@
}
/* Return the RAM size of the SOCRAM core */
-uint32 si_socram_size(si_t * sih)
+uint32 si_socram_size(si_t *sih)
{
si_info_t *sii;
uint origidx;
@@ -2682,7 +2682,7 @@
return memsize;
}
-void si_chipcontrl_epa4331(si_t * sih, bool on)
+void si_chipcontrl_epa4331(si_t *sih, bool on)
{
si_info_t *sii;
chipcregs_t *cc;
@@ -2716,7 +2716,7 @@
}
/* Enable BT-COEX & Ex-PA for 4313 */
-void si_epa_4313war(si_t * sih)
+void si_epa_4313war(si_t *sih)
{
si_info_t *sii;
chipcregs_t *cc;
@@ -2735,7 +2735,7 @@
}
/* check if the device is removed */
-bool si_deviceremoved(si_t * sih)
+bool si_deviceremoved(si_t *sih)
{
uint32 w;
si_info_t *sii;
@@ -2753,7 +2753,7 @@
return FALSE;
}
-bool si_is_sprom_available(si_t * sih)
+bool si_is_sprom_available(si_t *sih)
{
if (sih->ccrev >= 31) {
si_info_t *sii;
@@ -2790,7 +2790,7 @@
}
}
-bool si_is_otp_disabled(si_t * sih)
+bool si_is_otp_disabled(si_t *sih)
{
switch (CHIPID(sih->chip)) {
case BCM4329_CHIP_ID:
@@ -2818,14 +2818,14 @@
}
}
-bool si_is_otp_powered(si_t * sih)
+bool si_is_otp_powered(si_t *sih)
{
if (PMUCTL_ENAB(sih))
return si_pmu_is_otp_powered(sih, si_osh(sih));
return TRUE;
}
-void si_otp_power(si_t * sih, bool on)
+void si_otp_power(si_t *sih, bool on)
{
if (PMUCTL_ENAB(sih))
si_pmu_otp_power(sih, si_osh(sih), on);
@@ -2834,9 +2834,9 @@
bool
#if defined(BCMDBG)
-si_is_sprom_enabled(si_t * sih)
+si_is_sprom_enabled(si_t *sih)
#else
-BCMATTACHFN(si_is_sprom_enabled) (si_t * sih)
+BCMATTACHFN(si_is_sprom_enabled) (si_t *sih)
#endif
{
@@ -2845,9 +2845,9 @@
void
#if defined(BCMDBG)
-si_sprom_enable(si_t * sih, bool enable)
+si_sprom_enable(si_t *sih, bool enable)
#else
-BCMATTACHFN(si_sprom_enable) (si_t * sih, bool enable)
+BCMATTACHFN(si_sprom_enable) (si_t *sih, bool enable)
#endif
{
if (PMUCTL_ENAB(sih))
@@ -2855,7 +2855,7 @@
}
/* Return BCME_NOTFOUND if the card doesn't have CIS format nvram */
-int si_cis_source(si_t * sih)
+int si_cis_source(si_t *sih)
{
/* Many chips have the same mapping of their chipstatus field */
static const uint cis_sel[] =
diff --git a/drivers/staging/brcm80211/util/siutils_priv.h b/drivers/staging/brcm80211/util/siutils_priv.h
index b0c7803..51b8803 100644
--- a/drivers/staging/brcm80211/util/siutils_priv.h
+++ b/drivers/staging/brcm80211/util/siutils_priv.h
@@ -18,15 +18,15 @@
#define _siutils_priv_h_
/* Silicon Backplane externs */
-extern void sb_scan(si_t * sih, void *regs, uint devid);
-uint sb_coreid(si_t * sih);
-uint sb_corerev(si_t * sih);
-extern uint sb_corereg(si_t * sih, uint coreidx, uint regoff, uint mask,
+extern void sb_scan(si_t *sih, void *regs, uint devid);
+uint sb_coreid(si_t *sih);
+uint sb_corerev(si_t *sih);
+extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
uint val);
-extern bool sb_iscoreup(si_t * sih);
-void *sb_setcoreidx(si_t * sih, uint coreidx);
+extern bool sb_iscoreup(si_t *sih);
+void *sb_setcoreidx(si_t *sih, uint coreidx);
extern uint32 sb_base(uint32 admatch);
-extern void sb_core_reset(si_t * sih, uint32 bits, uint32 resetbits);
-extern void sb_core_disable(si_t * sih, uint32 bits);
-extern bool sb_taclear(si_t * sih, bool details);
+extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
+extern void sb_core_disable(si_t *sih, uint32 bits);
+extern bool sb_taclear(si_t *sih, bool details);
#endif /* _siutils_priv_h_ */