ARM: dts: msm: Add aggregate ufs phy axi clock for sdhc1 in sdm670
Sdhc1 controller in sdm670 require gcc_aggre_ufs_phy_axi_clk to be on
for ADMA to work. eMMC controller (sdhc1) requires this because, in
sdm670, the sdhc1 and ufs controllers share a common data path and the
common path uses the ufs_phy_axi clock. The use of UFS clock was
continued for the common path because of HW design considerations.
Change-Id: Ia09889228c73370278805a8e05c248ae21d8cd3a
Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org>
1 file changed