| commit | 7e81bda23ac3c79b6cf747c195810900b45a77fc | [log] [tgz] |
|---|---|---|
| author | Chen-Yu Tsai <wens@csie.org> | Thu Sep 15 23:14:01 2016 +0800 |
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | Sun Sep 18 21:13:35 2016 +0200 |
| tree | 0de412eee606239efcb7bc4cf87087316a518851 | |
| parent | e996e2089f25b84149ae82b5ddf37a263a7fcc71 [diff] |
drm/sun4i: dotclock: Allow divider = 127 The dot clock divider is 7 bits wide, and the divider range is 1 ~ 127, or 6 ~ 127 if phase offsets are used. The 0 register value also represents a divider of 1 or bypass. Make the end condition of the for loop inclusive of 127 in the round_rate callback. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>