msm: ipa: add support for new uC opcode
Support new uC opcode IPA_HDR_PROC_L2TP_HEADER_ADD
and IPA_HDR_PROC_L2TP_HEADER_REMOVE for L2TP.
Change-Id: Id0caddf76d06085f7ddaf52c7a48bd04a65f9069
Acked-by: Shihuan Liu <shihuanl@qti.qualcomm.com>
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c
index 6f46ebf..ae1b989 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c
@@ -1153,12 +1153,14 @@
* @phys_base: memory location in DDR
* @hdr_base_addr: base address in table
* @offset_entry: offset from hdr_base_addr in table
+ * @l2tp_params: l2tp parameters
*/
static int ipahal_cp_proc_ctx_to_hw_buff_v3(enum ipa_hdr_proc_type type,
void *const base, u32 offset,
u32 hdr_len, bool is_hdr_proc_ctx,
dma_addr_t phys_base, u32 hdr_base_addr,
- struct ipa_hdr_offset_entry *offset_entry){
+ struct ipa_hdr_offset_entry *offset_entry,
+ union ipa_l2tp_hdr_proc_ctx_params l2tp_params){
if (type == IPA_HDR_PROC_NONE) {
struct ipa_hw_hdr_proc_ctx_add_hdr_seq *ctx;
@@ -1174,6 +1176,58 @@
ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END;
ctx->end.length = 0;
ctx->end.value = 0;
+ } else if (type == IPA_HDR_PROC_L2TP_HEADER_ADD) {
+ struct ipa_hw_hdr_proc_ctx_add_l2tp_hdr_cmd_seq *ctx;
+
+ ctx = (struct ipa_hw_hdr_proc_ctx_add_l2tp_hdr_cmd_seq *)
+ (base + offset);
+ ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD;
+ ctx->hdr_add.tlv.length = 1;
+ ctx->hdr_add.tlv.value = hdr_len;
+ ctx->hdr_add.hdr_addr = is_hdr_proc_ctx ? phys_base :
+ hdr_base_addr + offset_entry->offset;
+ IPAHAL_DBG("header address 0x%x\n",
+ ctx->hdr_add.hdr_addr);
+ ctx->l2tp_params.tlv.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD;
+ ctx->l2tp_params.tlv.length = 1;
+ ctx->l2tp_params.tlv.value =
+ IPA_HDR_UCP_L2TP_HEADER_ADD;
+ ctx->l2tp_params.l2tp_params.eth_hdr_retained =
+ l2tp_params.hdr_add_param.eth_hdr_retained;
+ ctx->l2tp_params.l2tp_params.input_ip_version =
+ l2tp_params.hdr_add_param.input_ip_version;
+ ctx->l2tp_params.l2tp_params.output_ip_version =
+ l2tp_params.hdr_add_param.output_ip_version;
+
+ IPAHAL_DBG("command id %d\n", ctx->l2tp_params.tlv.value);
+ ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END;
+ ctx->end.length = 0;
+ ctx->end.value = 0;
+ } else if (type == IPA_HDR_PROC_L2TP_HEADER_REMOVE) {
+ struct ipa_hw_hdr_proc_ctx_remove_l2tp_hdr_cmd_seq *ctx;
+
+ ctx = (struct ipa_hw_hdr_proc_ctx_remove_l2tp_hdr_cmd_seq *)
+ (base + offset);
+ ctx->hdr_add.tlv.type = IPA_PROC_CTX_TLV_TYPE_HDR_ADD;
+ ctx->hdr_add.tlv.length = 1;
+ ctx->hdr_add.tlv.value = hdr_len;
+ ctx->hdr_add.hdr_addr = is_hdr_proc_ctx ? phys_base :
+ hdr_base_addr + offset_entry->offset;
+ IPAHAL_DBG("header address 0x%x length %d\n",
+ ctx->hdr_add.hdr_addr, ctx->hdr_add.tlv.value);
+ ctx->l2tp_params.tlv.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD;
+ ctx->l2tp_params.tlv.length = 1;
+ ctx->l2tp_params.tlv.value =
+ IPA_HDR_UCP_L2TP_HEADER_REMOVE;
+ ctx->l2tp_params.l2tp_params.hdr_len_remove =
+ l2tp_params.hdr_remove_param.hdr_len_remove;
+ ctx->l2tp_params.l2tp_params.eth_hdr_retained =
+ l2tp_params.hdr_remove_param.eth_hdr_retained;
+
+ IPAHAL_DBG("command id %d\n", ctx->l2tp_params.tlv.value);
+ ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END;
+ ctx->end.length = 0;
+ ctx->end.value = 0;
} else {
struct ipa_hw_hdr_proc_ctx_add_hdr_cmd_seq *ctx;
@@ -1242,7 +1296,8 @@
void *const base, u32 offset, u32 hdr_len,
bool is_hdr_proc_ctx, dma_addr_t phys_base,
u32 hdr_base_addr,
- struct ipa_hdr_offset_entry *offset_entry);
+ struct ipa_hdr_offset_entry *offset_entry,
+ union ipa_l2tp_hdr_proc_ctx_params l2tp_params);
int (*ipahal_get_proc_ctx_needed_len)(enum ipa_hdr_proc_type type);
};
@@ -1307,11 +1362,13 @@
* @phys_base: memory location in DDR
* @hdr_base_addr: base address in table
* @offset_entry: offset from hdr_base_addr in table
+ * @l2tp_params: l2tp parameters
*/
int ipahal_cp_proc_ctx_to_hw_buff(enum ipa_hdr_proc_type type,
void *const base, u32 offset, u32 hdr_len,
bool is_hdr_proc_ctx, dma_addr_t phys_base,
- u32 hdr_base_addr, struct ipa_hdr_offset_entry *offset_entry)
+ u32 hdr_base_addr, struct ipa_hdr_offset_entry *offset_entry,
+ union ipa_l2tp_hdr_proc_ctx_params l2tp_params)
{
IPAHAL_DBG(
"type %d, base %p, offset %d, hdr_len %d, is_hdr_proc_ctx %d, hdr_base_addr %d, offset_entry %p\n"
@@ -1332,7 +1389,7 @@
return hdr_funcs.ipahal_cp_proc_ctx_to_hw_buff(type, base, offset,
hdr_len, is_hdr_proc_ctx, phys_base,
- hdr_base_addr, offset_entry);
+ hdr_base_addr, offset_entry, l2tp_params);
}
/*