tree 2dcd8489f27b51dcdf99fe43267262ae80aced1a
parent 836a8ac9fe60fb112e830464868791bf7470e7b6
author Thierry Reding <treding@nvidia.com> 1427450847 +0100
committer Joerg Roedel <jroedel@suse.de> 1427812535 +0200

iommu/tegra: smmu: Compute PFN mask at runtime

The SMMU on Tegra30 and Tegra114 supports addressing up to 4 GiB of
physical memory. On Tegra124 the addressable physical memory was
extended to 16 GiB. The page frame number stored in PTEs therefore
requires 20 or 22 bits, depending on SoC generation.

In order to cope with this, compute the proper value at runtime.

Reported-by: Joseph Lo <josephl@nvidia.com>
Cc: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>