| commit | 81c7e03acbcb68274be770134f8f04f270ffa859 | [log] [tgz] |
|---|---|---|
| author | Peter Ujfalusi <peter.ujfalusi@ti.com> | Wed Apr 30 14:39:37 2014 +0300 |
| committer | Tero Kristo <t-kristo@ti.com> | Fri Jun 06 20:33:34 2014 +0300 |
| tree | ca6115715324f00441d89cc4a08e6a6382b48687 | |
| parent | 9ac33b0ce81fa48dd39e7ddfc1bf4519052181dd [diff] |
CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ck In order to get correct clock dividers for AESS/ABE we need to set the dpll_abe_m2x2_ck rate to be double of dpll_abe_ck. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>