tree ca6115715324f00441d89cc4a08e6a6382b48687
parent 9ac33b0ce81fa48dd39e7ddfc1bf4519052181dd
author Peter Ujfalusi <peter.ujfalusi@ti.com> 1398857977 +0300
committer Tero Kristo <t-kristo@ti.com> 1402076014 +0300

CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ck

In order to get correct clock dividers for AESS/ABE we need to set the
dpll_abe_m2x2_ck rate to be double of dpll_abe_ck.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>