tree e7240d24e566664e5120a8adc582d73f96d8c5fb
parent b2faf1a1aff945ec2abf2efdd9002c96b25378e8
author Gary Bisson <bisson.gary@gmail.com> 1417647831 -0800
committer Shawn Guo <shawn.guo@linaro.org> 1419852214 +0800

ARM: clk-imx6q: fix video divider for rev T0 1.0

The post dividers do not work on i.MX6Q rev T0 1.0 so they must be fixed
to 1. As the table index was wrong, a divider a of 4 could still be
requested which implied the clock not to be set properly. This is the
root cause of the HDMI not working at high resolution on rev T0 1.0 of
the SoC.

Signed-off-by: Gary Bisson <bisson.gary@gmail.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>