drm/msm/sde: add restore functionality after idle power collapse
During the idle_PC state all the registers are wiped out as
all the resources are disabled. The CRTC registers for the
MDP core clock enable event and restores all the register
configurations in CRTC, encoder and planes.
Change-Id: I48895899f3a0491f4dc0ad5cec66fc7c7c47da7f
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c
index 0e257f1..7a0c8d7 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.c
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.c
@@ -2190,21 +2190,62 @@
return 0;
}
+static void sde_crtc_handle_power_event(u32 event_type, void *arg)
+{
+ struct drm_crtc *crtc = arg;
+ struct sde_crtc *sde_crtc;
+ struct drm_encoder *encoder;
+
+ if (!crtc) {
+ SDE_ERROR("invalid crtc\n");
+ return;
+ }
+ sde_crtc = to_sde_crtc(crtc);
+
+ mutex_lock(&sde_crtc->crtc_lock);
+
+ SDE_EVT32(DRMID(crtc), event_type);
+
+ if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
+ /* restore encoder; crtc will be programmed during commit */
+ drm_for_each_encoder(encoder, crtc->dev) {
+ if (encoder->crtc != crtc)
+ continue;
+
+ sde_encoder_virt_restore(encoder);
+ }
+
+ } else if (event_type == SDE_POWER_EVENT_POST_DISABLE) {
+ struct drm_plane *plane;
+
+ /*
+ * set revalidate flag in planes, so it will be re-programmed
+ * in the next frame update
+ */
+ drm_atomic_crtc_for_each_plane(plane, crtc)
+ sde_plane_set_revalidate(plane, true);
+ }
+
+ mutex_unlock(&sde_crtc->crtc_lock);
+}
+
static void sde_crtc_disable(struct drm_crtc *crtc)
{
struct sde_crtc *sde_crtc;
struct sde_crtc_state *cstate;
struct drm_encoder *encoder;
+ struct msm_drm_private *priv;
unsigned long flags;
struct sde_crtc_irq_info *node = NULL;
int ret;
- if (!crtc || !crtc->dev || !crtc->state) {
+ if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
SDE_ERROR("invalid crtc\n");
return;
}
sde_crtc = to_sde_crtc(crtc);
cstate = to_sde_crtc_state(crtc->state);
+ priv = crtc->dev->dev_private;
SDE_DEBUG("crtc%d\n", crtc->base.id);
@@ -2244,6 +2285,10 @@
cstate->rsc_update = false;
}
+ if (sde_crtc->power_event)
+ sde_power_handle_unregister_event(&priv->phandle,
+ sde_crtc->power_event);
+
memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
sde_crtc->num_mixers = 0;
@@ -2265,14 +2310,16 @@
{
struct sde_crtc *sde_crtc;
struct drm_encoder *encoder;
+ struct msm_drm_private *priv;
unsigned long flags;
struct sde_crtc_irq_info *node = NULL;
int ret;
- if (!crtc) {
+ if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
SDE_ERROR("invalid crtc\n");
return;
}
+ priv = crtc->dev->dev_private;
SDE_DEBUG("crtc%d\n", crtc->base.id);
SDE_EVT32(DRMID(crtc));
@@ -2295,6 +2342,11 @@
sde_crtc->name, node->event);
}
spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
+
+ sde_crtc->power_event = sde_power_handle_register_event(
+ &priv->phandle,
+ SDE_POWER_EVENT_POST_ENABLE | SDE_POWER_EVENT_POST_DISABLE,
+ sde_crtc_handle_power_event, crtc, sde_crtc->name);
}
struct plane_state {
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.h b/drivers/gpu/drm/msm/sde/sde_crtc.h
index 4bf0300..ec5ec1d 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.h
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.h
@@ -138,6 +138,7 @@
* @event_free_list : List of available event structures
* @event_lock : Spinlock around event handling code
* @misr_enable : boolean entry indicates misr enable/disable status.
+ * @power_event : registered power event handle
*/
struct sde_crtc {
struct drm_crtc base;
@@ -187,6 +188,8 @@
struct list_head event_free_list;
spinlock_t event_lock;
bool misr_enable;
+
+ struct sde_power_event *power_event;
};
#define to_sde_crtc(x) container_of(x, struct sde_crtc, base)
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.c b/drivers/gpu/drm/msm/sde/sde_encoder.c
index 3b034dd..cd428cf 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.c
@@ -1169,34 +1169,79 @@
}
}
-static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
+static void _sde_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
{
struct sde_encoder_virt *sde_enc = NULL;
struct msm_drm_private *priv;
struct sde_kms *sde_kms;
- int i = 0;
int ret = 0;
- if (!drm_enc) {
- SDE_ERROR("invalid encoder\n");
+ if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
+ SDE_ERROR("invalid parameters\n");
return;
- } else if (!drm_enc->dev) {
- SDE_ERROR("invalid dev\n");
- return;
- } else if (!drm_enc->dev->dev_private) {
- SDE_ERROR("invalid dev_private\n");
+ }
+ priv = drm_enc->dev->dev_private;
+
+ sde_enc = to_sde_encoder_virt(drm_enc);
+ if (!sde_enc || !sde_enc->cur_master) {
+ SDE_ERROR("invalid sde encoder/master\n");
return;
}
- sde_enc = to_sde_encoder_virt(drm_enc);
- priv = drm_enc->dev->dev_private;
sde_kms = to_sde_kms(priv->kms);
-
if (!sde_kms) {
SDE_ERROR("invalid sde_kms\n");
return;
}
+ if (sde_enc->cur_master->hw_mdptop &&
+ sde_enc->cur_master->hw_mdptop->ops.reset_ubwc)
+ sde_enc->cur_master->hw_mdptop->ops.reset_ubwc(
+ sde_enc->cur_master->hw_mdptop,
+ sde_kms->catalog);
+
+ if (_sde_is_dsc_enabled(sde_enc)) {
+ ret = _sde_encoder_dsc_setup(sde_enc);
+ if (ret)
+ SDE_ERROR_ENC(sde_enc, "failed to setup DSC:%d\n", ret);
+ }
+}
+
+void sde_encoder_virt_restore(struct drm_encoder *drm_enc)
+{
+ struct sde_encoder_virt *sde_enc = NULL;
+ int i;
+
+ if (!drm_enc) {
+ SDE_ERROR("invalid encoder\n");
+ return;
+ }
+ sde_enc = to_sde_encoder_virt(drm_enc);
+
+ for (i = 0; i < sde_enc->num_phys_encs; i++) {
+ struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+ if (phys && (phys != sde_enc->cur_master) && phys->ops.restore)
+ phys->ops.restore(phys);
+ }
+
+ if (sde_enc->cur_master && sde_enc->cur_master->ops.restore)
+ sde_enc->cur_master->ops.restore(sde_enc->cur_master);
+
+ _sde_encoder_virt_enable_helper(drm_enc);
+}
+
+static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
+{
+ struct sde_encoder_virt *sde_enc = NULL;
+ int i, ret = 0;
+
+ if (!drm_enc) {
+ SDE_ERROR("invalid encoder\n");
+ return;
+ }
+ sde_enc = to_sde_encoder_virt(drm_enc);
+
SDE_DEBUG_ENC(sde_enc, "\n");
SDE_EVT32(DRMID(drm_enc));
@@ -1230,21 +1275,10 @@
phys->ops.enable(phys);
}
- if (sde_enc->cur_master && sde_enc->cur_master->ops.enable)
+ if (sde_enc->cur_master->ops.enable)
sde_enc->cur_master->ops.enable(sde_enc->cur_master);
- if (sde_enc->cur_master && sde_enc->cur_master->hw_mdptop &&
- sde_enc->cur_master->hw_mdptop->ops.reset_ubwc)
- sde_enc->cur_master->hw_mdptop->ops.reset_ubwc(
- sde_enc->cur_master->hw_mdptop,
- sde_kms->catalog);
-
- if (_sde_is_dsc_enabled(sde_enc)) {
- ret = _sde_encoder_dsc_setup(sde_enc);
- if (ret)
- SDE_ERROR_ENC(sde_enc, "failed to setup DSC: %d\n",
- ret);
- }
+ _sde_encoder_virt_enable_helper(drm_enc);
}
static void sde_encoder_virt_disable(struct drm_encoder *drm_enc)
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.h b/drivers/gpu/drm/msm/sde/sde_encoder.h
index ad63487..bd3d68b 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.h
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.h
@@ -127,6 +127,12 @@
enum sde_intf_mode sde_encoder_get_intf_mode(struct drm_encoder *encoder);
/**
+ * sde_encoder_virt_restore - restore the encoder configs
+ * @encoder: encoder pointer
+ */
+void sde_encoder_virt_restore(struct drm_encoder *encoder);
+
+/**
* enum sde_encoder_property - property tags for sde enoder
* @SDE_ENCODER_PROPERTY_INLINE_ROTATE_REFILL: # of prefill line, 0 to disable
*/
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys.h b/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
index f7fe90d..a73113f 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
@@ -121,6 +121,7 @@
* SDE_ENC_ERR_NEEDS_HW_RESET state
* @irq_control: Handler to enable/disable all the encoder IRQs
* @update_split_role: Update the split role of the phys enc
+ * @restore: Restore all the encoder configs.
*/
struct sde_encoder_phys_ops {
@@ -157,6 +158,7 @@
void (*irq_control)(struct sde_encoder_phys *phys, bool enable);
void (*update_split_role)(struct sde_encoder_phys *phys_enc,
enum sde_enc_split_role role);
+ void (*restore)(struct sde_encoder_phys *phys);
};
/**
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
index 799015f..3e83146 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
@@ -582,10 +582,9 @@
return _sde_encoder_phys_is_ppsplit(phys_enc);
}
-static void sde_encoder_phys_cmd_enable(struct sde_encoder_phys *phys_enc)
+static void sde_encoder_phys_cmd_enable_helper(
+ struct sde_encoder_phys *phys_enc)
{
- struct sde_encoder_phys_cmd *cmd_enc =
- to_sde_encoder_phys_cmd(phys_enc);
struct sde_hw_ctl *ctl;
u32 flush_mask = 0;
@@ -593,12 +592,6 @@
SDE_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
return;
}
- SDE_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
-
- if (phys_enc->enable_state == SDE_ENC_ENABLED) {
- SDE_ERROR("already enabled\n");
- return;
- }
sde_encoder_helper_split_config(phys_enc, phys_enc->intf_idx);
@@ -607,7 +600,25 @@
ctl = phys_enc->hw_ctl;
ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->intf_idx);
ctl->ops.update_pending_flush(ctl, flush_mask);
+}
+static void sde_encoder_phys_cmd_enable(struct sde_encoder_phys *phys_enc)
+{
+ struct sde_encoder_phys_cmd *cmd_enc =
+ to_sde_encoder_phys_cmd(phys_enc);
+
+ if (!phys_enc) {
+ SDE_ERROR("invalid phys encoder\n");
+ return;
+ }
+ SDE_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
+
+ if (phys_enc->enable_state == SDE_ENC_ENABLED) {
+ SDE_ERROR("already enabled\n");
+ return;
+ }
+
+ sde_encoder_phys_cmd_enable_helper(phys_enc);
phys_enc->enable_state = SDE_ENC_ENABLED;
}
@@ -760,6 +771,7 @@
ops->hw_reset = sde_encoder_helper_hw_reset;
ops->irq_control = sde_encoder_phys_cmd_irq_control;
ops->update_split_role = sde_encoder_phys_cmd_update_split_role;
+ ops->restore = sde_encoder_phys_cmd_enable_helper;
}
struct sde_encoder_phys *sde_encoder_phys_cmd_init(
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c
index 93268be..c408861 100644
--- a/drivers/gpu/drm/msm/sde/sde_plane.c
+++ b/drivers/gpu/drm/msm/sde/sde_plane.c
@@ -75,12 +75,6 @@
#define TX_MODE_BUFFER_LINE_THRES 2
-/* dirty bits for update function */
-#define SDE_PLANE_DIRTY_RECTS 0x1
-#define SDE_PLANE_DIRTY_FORMAT 0x2
-#define SDE_PLANE_DIRTY_SHARPEN 0x4
-#define SDE_PLANE_DIRTY_ALL 0xFFFFFFFF
-
#define SDE_QSEED3_DEFAULT_PRELOAD_H 0x4
#define SDE_QSEED3_DEFAULT_PRELOAD_V 0x3
@@ -107,7 +101,8 @@
* @csc_ptr: Points to sde_csc_cfg structure to use for current
* @catalog: Points to sde catalog structure
* @sbuf_mode: force stream buffer mode if set
- * @sbuf_writeback: fource stream buffer writeback if set
+ * @sbuf_writeback: force stream buffer writeback if set
+ * @revalidate: force revalidation of all the plane properties
* @blob_rot_caps: Pointer to rotator capability blob
*/
struct sde_plane {
@@ -134,6 +129,7 @@
struct sde_mdss_cfg *catalog;
u32 sbuf_mode;
u32 sbuf_writeback;
+ bool revalidate;
struct sde_hw_pixel_ext pixel_ext;
bool pixel_ext_usr;
@@ -499,6 +495,17 @@
&psde->pipe_qos_cfg);
}
+void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
+{
+ struct sde_plane *psde;
+
+ if (!plane)
+ return;
+
+ psde = to_sde_plane(plane);
+ psde->revalidate = enable;
+}
+
int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
{
struct sde_plane *psde;
@@ -2250,6 +2257,14 @@
state->crtc_w, state->crtc_h,
state->crtc_x, state->crtc_y);
+ /* force reprogramming of all the parameters, if the flag is set */
+ if (psde->revalidate) {
+ SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
+ plane->base.id);
+ pstate->dirty = SDE_PLANE_DIRTY_ALL;
+ psde->revalidate = false;
+ }
+
/* determine what needs to be refreshed */
while ((idx = msm_property_pop_dirty(&psde->property_info)) >= 0) {
switch (idx) {
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.h b/drivers/gpu/drm/msm/sde/sde_plane.h
index e955f41..ac70542 100644
--- a/drivers/gpu/drm/msm/sde/sde_plane.h
+++ b/drivers/gpu/drm/msm/sde/sde_plane.h
@@ -91,6 +91,12 @@
int out_xpos;
};
+/* dirty bits for update function */
+#define SDE_PLANE_DIRTY_RECTS 0x1
+#define SDE_PLANE_DIRTY_FORMAT 0x2
+#define SDE_PLANE_DIRTY_SHARPEN 0x4
+#define SDE_PLANE_DIRTY_ALL 0xFFFFFFFF
+
/**
* struct sde_plane_state: Define sde extension of drm plane state object
* @base: base drm plane state object
@@ -222,4 +228,12 @@
int sde_plane_color_fill(struct drm_plane *plane,
uint32_t color, uint32_t alpha);
+/**
+ * sde_plane_set_revalidate - sets revalidate flag which forces a full
+ * validation of the plane properties in the next atomic check
+ * @plane: Pointer to DRM plane object
+ * @enable: Boolean to set/unset the flag
+ */
+void sde_plane_set_revalidate(struct drm_plane *plane, bool enable);
+
#endif /* _SDE_PLANE_H_ */