| commit | d0e4120fda6f87eead438eed4d49032e12060e58 | [log] [tgz] |
|---|---|---|
| author | Robert Richter <robert.richter@amd.com> | Tue Mar 23 19:33:21 2010 +0100 |
| committer | Robert Richter <robert.richter@amd.com> | Tue May 04 11:35:26 2010 +0200 |
| tree | 57f3ab727aa12bc63f19437a0a026e2ea5bd6d67 | |
| parent | 8f5a2dd83a1f8e89fdc17eb0f2f07c2e713e635a [diff] |
oprofile/x86: reserve counter msrs pairwise For AMD's and Intel's P6 generic performance counters have pairwise counter and control msrs. This patch changes the counter reservation in a way that both msrs must be registered. It joins some counter loops and also removes the unnecessary NUM_CONTROLS macro in the AMD implementation. Signed-off-by: Robert Richter <robert.richter@amd.com>