commit 836a8051d54525e0782f156dcfa3c13d30f22840
author Stanislav Samsonov <samsonov@marvell.com> Tue Jun 03 11:24:40 2008 +0300
committer Lennert Buytenhek <buytenh@marvell.com> Sun Jun 22 22:45:03 2008 +0200
tree a72c16e6bbfb4b4768562bc9757bdd04b17e4c7f
parent 7ea217a85e38c5ed6edbc789670badb619da9f28

[ARM] Feroceon: L1 cache range operation support

This patch adds support for the L1 D cache range operations that
are supported by the Marvell Discovery Duo and Marvell Kirkwood
ARM SoCs.

Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Acked-by: Saeed Bishara <saeed@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>

include/asm-arm/cacheflush.h

diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 759a97b..b85d426 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -95,11 +95,7 @@
 #endif
 
 #if defined(CONFIG_CPU_FEROCEON)
-# ifdef _CACHE
-#  define MULTI_CACHE 1
-# else
-#  define _CACHE feroceon
-# endif
+# define MULTI_CACHE 1
 #endif
 
 #if defined(CONFIG_CPU_V6)