83e27fcdee0fbb59a4f5dc148edf088f6806bdb9 - kernel/msm-4.9

commit	83e27fcdee0fbb59a4f5dc148edf088f6806bdb9	[log] [tgz]
author	Dhaval Patel <pdhaval@codeaurora.org>	Thu Dec 19 14:52:24 2013 -0800
committer	Narendra Muppalla <NarendraM@codeaurora.org>	Fri Jan 13 15:29:05 2017 -0800
tree	6eef3ff0b05cbff76d790fc0525fa750f5aa1e14
parent	9583cdc900b475b6bdbf1d35545d61719717f7eb [diff]

clk: qcom: mdss: Add mdss pll clock driver support

Each display output interface such as eDP, HDMI and
DSI are clocked by different pll clocks to support
various displays at different resolution simultaneously.
The mdss pll driver handles all these display output
interfaces' pll clocks separately. It also handles their
resources through dtsi configuration.

Change-Id: I1de2ae9a0549de901a6c82ea489199a722344dc4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Signed-off-by: Narendra Muppalla <narendram@codeaurora.org>

Documentation/devicetree/bindings/fb/mdss-pll.txt[Added - diff]
drivers/clk/qcom/mdss/Kconfig[Added - diff]
drivers/clk/qcom/mdss/Makefile[Added - diff]
drivers/clk/qcom/mdss/mdss-dsi-pll-28hpm.c[Added - diff]
drivers/clk/qcom/mdss/mdss-dsi-pll.h[Added - diff]
drivers/clk/qcom/mdss/mdss-edp-pll-28hpm.c[Added - diff]
drivers/clk/qcom/mdss/mdss-edp-pll.h[Added - diff]
drivers/clk/qcom/mdss/mdss-hdmi-pll-28hpm.c[Added - diff]
drivers/clk/qcom/mdss/mdss-hdmi-pll.h[Added - diff]
drivers/clk/qcom/mdss/mdss-pll-util.c[Added - diff]
drivers/clk/qcom/mdss/mdss-pll.c[Added - diff]
drivers/clk/qcom/mdss/mdss-pll.h[Added - diff]

12 files changed

tree: 6eef3ff0b05cbff76d790fc0525fa750f5aa1e14