| commit | 847b9dfccad7dd34b2e44b1c6ceeb1c4cb88084a | [log] [tgz] |
|---|---|---|
| author | Chris Dearman <chris@mips.com> | Mon Aug 07 15:08:01 2006 +0100 |
| committer | Ralf Baechle <ralf@linux-mips.org> | Wed Sep 27 13:37:33 2006 +0100 |
| tree | 46374a118b2f42c17aef00ec478021043e56e38b | |
| parent | bca70d24c09b740d6fd96b972011644cba8383d6 [diff] |
[MIPS] MT: Initialise all writable bits in Cause register to zero. Recent 34Ks come out of reset with WP enabled on VPE 1 so we take an immediate exception when starting the second VPE. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>