x86/oprofile: add CONFIG_OPROFILE_IBS option
Signed-off-by: Robert Richter <robert.richter@amd.com>
Cc: oprofile-list <oprofile-list@lists.sourceforge.net>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Barry Kasindorf <barry.kasindorf@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/arch/x86/oprofile/op_model_athlon.c b/arch/x86/oprofile/op_model_athlon.c
index 9c8c8c5..fb6015c 100644
--- a/arch/x86/oprofile/op_model_athlon.c
+++ b/arch/x86/oprofile/op_model_athlon.c
@@ -47,6 +47,10 @@
#define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
#define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
+static unsigned long reset_value[NUM_COUNTERS];
+
+#ifdef CONFIG_OPROFILE_IBS
+
/* IbsFetchCtl bits/masks */
#define IBS_FETCH_HIGH_VALID_BIT (1UL << 17) /* bit 49 */
#define IBS_FETCH_HIGH_ENABLE (1UL << 16) /* bit 48 */
@@ -104,7 +108,6 @@
*/
static void clear_ibs_nmi(void);
-static unsigned long reset_value[NUM_COUNTERS];
static int ibs_allowed; /* AMD Family10h and later */
struct op_ibs_config {
@@ -118,6 +121,8 @@
static struct op_ibs_config ibs_config;
+#endif
+
/* functions for op_amd_spec */
static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
@@ -188,6 +193,8 @@
}
}
+#ifdef CONFIG_OPROFILE_IBS
+
static inline int
op_amd_handle_ibs(struct pt_regs * const regs,
struct op_msrs const * const msrs)
@@ -261,6 +268,8 @@
return 1;
}
+#endif
+
static int op_amd_check_ctrs(struct pt_regs * const regs,
struct op_msrs const * const msrs)
{
@@ -277,7 +286,9 @@
}
}
+#ifdef CONFIG_OPROFILE_IBS
op_amd_handle_ibs(regs, msrs);
+#endif
/* See op_model_ppro.c */
return 1;
@@ -294,6 +305,8 @@
CTRL_WRITE(low, high, msrs, i);
}
}
+
+#ifdef CONFIG_OPROFILE_IBS
if (ibs_allowed && ibs_config.fetch_enabled) {
low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
high = IBS_FETCH_HIGH_ENABLE;
@@ -305,6 +318,7 @@
high = 0;
wrmsr(MSR_AMD64_IBSOPCTL, low, high);
}
+#endif
}
@@ -323,6 +337,7 @@
CTRL_WRITE(low, high, msrs, i);
}
+#ifdef CONFIG_OPROFILE_IBS
if (ibs_allowed && ibs_config.fetch_enabled) {
low = 0; /* clear max count and enable */
high = 0;
@@ -334,6 +349,7 @@
high = 0;
wrmsr(MSR_AMD64_IBSOPCTL, low, high);
}
+#endif
}
static void op_amd_shutdown(struct op_msrs const * const msrs)
@@ -350,17 +366,10 @@
}
}
-#ifndef CONFIG_SMP
+#ifndef CONFIG_OPROFILE_IBS
/* no IBS support */
-static void setup_ibs(void)
-{
- ibs_allowed = 0;
-}
-
-static void clear_ibs_nmi(void) {}
-
static int op_amd_init(struct oprofile_operations *ops)
{
return 0;
@@ -441,8 +450,12 @@
if (!ibs_allowed)
return;
- if (pfm_amd64_setup_eilvt())
+ if (pfm_amd64_setup_eilvt()) {
ibs_allowed = 0;
+ return;
+ }
+
+ printk(KERN_INFO "oprofile: AMD IBS detected\n");
}