tree 3f2a198c4c69346656611fe284c17f8a42080541
parent f2032d413a2d47089f2b3f8fdd0e344a04de8195
author Dave Airlie <airlied@redhat.com> 1348017161 +1000
committer Dave Airlie <airlied@gmail.com> 1348048766 +1000

drm: micro optimise cache flushing

We hit this a lot with i915 and although we'd like to engineer things to hit
it a lot less, this commit at least makes it consume a few less cycles.

from something containing
movzwl 0x0(%rip),%r10d
to
add    %r8,%rdx

I only noticed it while using perf to profile something else.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Dave Airlie <airlied@redhat.com>