drivers: add a snapshot of various QPNP PMIC peripheral drivers
Add a snapshot of several Qualcomm Technologies, Inc. QPNP PMIC
peripheral drivers. These drivers manage various modules found
within PMIC chips.
This snapshot is taken as of msm-4.4
commit d24550bbf50f ("Merge "ARM: dts: msm: Add slimbus slave
device for wcn3990 on sdm630"").
Change-Id: I842f81737eec1ca11bf31534e9299bd7a6511f6c
Signed-off-by: David Collins <collinsd@codeaurora.org>
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 96a816d..534a1d7 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -988,6 +988,35 @@
the higher ones by BHS. This driver allows for configuration of
the rail between the LDO/BHS as well as the LDO voltage.
+config REGULATOR_QPNP_LABIBB
+ tristate "Qualcomm Technologies, Inc. QPNP LAB/IBB regulator support"
+ depends on SPMI
+ help
+ This driver supports voltage regulators in Qualcomm Technologies, Inc.
+ PMIC chips which comply with QPNP LAB/IBB regulators. QPNP LAB and IBB
+ are SPMI based PMIC implementations. LAB regulator can be used as a
+ regular positive boost regulator. IBB can be used as a regular
+ negative boost regulator. LAB/IBB regulators can also be used
+ together for LCD or AMOLED.
+
+config REGULATOR_QPNP_LCDB
+ tristate "Qualcomm Technologies, Inc. QPNP LCDB support"
+ depends on SPMI
+ help
+ Supports the LCDB module in the Qualcomm Technologies, Inc.
+ QPNP PMICs. Exposes regulators to control the positive and
+ negative voltage bias for the LCD display panel. It also
+ allows configurability for the various bias-voltage parameters.
+
+config REGULATOR_QPNP_OLEDB
+ tristate "Qualcomm Technologies, Inc. QPNP OLEDB regulator support"
+ depends on SPMI
+ help
+ This driver supports the OLEDB (AVDD bias) signal for AMOLED panel in
+ Qualcomm Technologies, Inc. QPNP PMICs. It exposes the OLED voltage
+ configuration via the regulator framework. The configurable range of
+ this bias is 5 V to 8.1 V.
+
config REGULATOR_QPNP
tristate "Qualcomm Technologies, Inc. QPNP regulator support"
depends on SPMI
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 1a96c07..bf30b8d 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -123,6 +123,9 @@
obj-$(CONFIG_REGULATOR_KRYO) += kryo-regulator.o
obj-$(CONFIG_REGULATOR_MEM_ACC) += mem-acc-regulator.o
obj-$(CONFIG_REGULATOR_MSM_GFX_LDO) += msm_gfx_ldo.o
+obj-$(CONFIG_REGULATOR_QPNP_LABIBB) += qpnp-labibb-regulator.o
+obj-$(CONFIG_REGULATOR_QPNP_LCDB) += qpnp-lcdb-regulator.o
+obj-$(CONFIG_REGULATOR_QPNP_OLEDB) += qpnp-oledb-regulator.o
obj-$(CONFIG_REGULATOR_QPNP) += qpnp-regulator.o
obj-$(CONFIG_REGULATOR_RPMH) += rpmh-regulator.o
obj-$(CONFIG_REGULATOR_STUB) += stub-regulator.o
diff --git a/drivers/regulator/qpnp-labibb-regulator.c b/drivers/regulator/qpnp-labibb-regulator.c
new file mode 100644
index 0000000..cf8f000
--- /dev/null
+++ b/drivers/regulator/qpnp-labibb-regulator.c
@@ -0,0 +1,3877 @@
+/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/regmap.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/spmi.h>
+#include <linux/platform_device.h>
+#include <linux/string.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/qpnp/qpnp-revid.h>
+
+#define QPNP_LABIBB_REGULATOR_DRIVER_NAME "qcom,qpnp-labibb-regulator"
+
+#define REG_REVISION_2 0x01
+#define REG_PERPH_TYPE 0x04
+
+#define QPNP_LAB_TYPE 0x24
+#define QPNP_IBB_TYPE 0x20
+
+/* Common register value for LAB/IBB */
+#define REG_LAB_IBB_LCD_MODE 0x0
+#define REG_LAB_IBB_AMOLED_MODE BIT(7)
+#define REG_LAB_IBB_SEC_ACCESS 0xD0
+#define REG_LAB_IBB_SEC_UNLOCK_CODE 0xA5
+
+/* LAB register offset definitions */
+#define REG_LAB_STATUS1 0x08
+#define REG_LAB_SWIRE_PGM_CTL 0x40
+#define REG_LAB_VOLTAGE 0x41
+#define REG_LAB_RING_SUPPRESSION_CTL 0x42
+#define REG_LAB_LCD_AMOLED_SEL 0x44
+#define REG_LAB_MODULE_RDY 0x45
+#define REG_LAB_ENABLE_CTL 0x46
+#define REG_LAB_PD_CTL 0x47
+#define REG_LAB_CLK_DIV 0x48
+#define REG_LAB_IBB_EN_RDY 0x49
+#define REG_LAB_CURRENT_LIMIT 0x4B
+#define REG_LAB_CURRENT_SENSE 0x4C
+#define REG_LAB_PS_CTL 0x50
+#define REG_LAB_RDSON_MNGMNT 0x53
+#define REG_LAB_PRECHARGE_CTL 0x5E
+#define REG_LAB_SOFT_START_CTL 0x5F
+#define REG_LAB_SPARE_CTL 0x60
+#define REG_LAB_PFM_CTL 0x62
+
+/* LAB registers for PM660A */
+#define REG_LAB_VOUT_DEFAULT 0x44
+#define REG_LAB_SW_HIGH_PSRR_CTL 0x70
+#define REG_LAB_LDO_PD_CTL 0x78
+#define REG_LAB_VPH_ENVELOP_CTL 0x7E
+
+/* LAB register bits definitions */
+
+/* REG_LAB_STATUS1 */
+#define LAB_STATUS1_VREG_OK_MASK BIT(7)
+#define LAB_STATUS1_VREG_OK BIT(7)
+
+/* REG_LAB_SWIRE_PGM_CTL */
+#define LAB_EN_SWIRE_PGM_VOUT BIT(7)
+#define LAB_EN_SWIRE_PGM_PD BIT(6)
+
+/* REG_LAB_VOLTAGE */
+#define LAB_VOLTAGE_OVERRIDE_EN BIT(7)
+#define LAB_VOLTAGE_SET_MASK GENMASK(3, 0)
+
+/* REG_LAB_RING_SUPPRESSION_CTL */
+#define LAB_RING_SUPPRESSION_CTL_EN BIT(7)
+
+/* REG_LAB_MODULE_RDY */
+#define LAB_MODULE_RDY_EN BIT(7)
+
+/* REG_LAB_ENABLE_CTL */
+#define LAB_ENABLE_CTL_EN BIT(7)
+
+/* REG_LAB_PD_CTL */
+#define LAB_PD_CTL_STRONG_PULL BIT(0)
+#define LAB_PD_CTL_STRENGTH_MASK BIT(0)
+#define LAB_PD_CTL_DISABLE_PD BIT(1)
+#define LAB_PD_CTL_EN_MASK BIT(1)
+
+/* REG_LAB_IBB_EN_RDY */
+#define LAB_IBB_EN_RDY_EN BIT(7)
+
+/* REG_LAB_CURRENT_LIMIT */
+#define LAB_CURRENT_LIMIT_MASK GENMASK(2, 0)
+#define LAB_CURRENT_LIMIT_EN_BIT BIT(7)
+#define LAB_OVERRIDE_CURRENT_MAX_BIT BIT(3)
+
+/* REG_LAB_CURRENT_SENSE */
+#define LAB_CURRENT_SENSE_GAIN_MASK GENMASK(1, 0)
+
+/* REG_LAB_PS_CTL */
+#define LAB_PS_THRESH_MASK GENMASK(1, 0)
+#define LAB_PS_CTL_EN BIT(7)
+
+/* REG_LAB_RDSON_MNGMNT */
+#define LAB_RDSON_MNGMNT_NFET_SLEW_EN BIT(5)
+#define LAB_RDSON_MNGMNT_PFET_SLEW_EN BIT(4)
+#define LAB_RDSON_MNGMNT_NFET_MASK GENMASK(3, 2)
+#define LAB_RDSON_MNGMNT_NFET_SHIFT 2
+#define LAB_RDSON_MNGMNT_PFET_MASK GENMASK(1, 0)
+#define LAB_RDSON_NFET_SW_SIZE_QUARTER 0x0
+#define LAB_RDSON_PFET_SW_SIZE_QUARTER 0x0
+
+/* REG_LAB_PRECHARGE_CTL */
+#define LAB_FAST_PRECHARGE_CTL_EN BIT(2)
+#define LAB_MAX_PRECHARGE_TIME_MASK GENMASK(1, 0)
+
+/* REG_LAB_SOFT_START_CTL */
+#define LAB_SOFT_START_CTL_MASK GENMASK(1, 0)
+
+/* REG_LAB_SPARE_CTL */
+#define LAB_SPARE_TOUCH_WAKE_BIT BIT(3)
+#define LAB_SPARE_DISABLE_SCP_BIT BIT(0)
+
+/* REG_LAB_PFM_CTL */
+#define LAB_PFM_EN_BIT BIT(7)
+
+/* REG_LAB_SW_HIGH_PSRR_CTL */
+#define LAB_EN_SW_HIGH_PSRR_MODE BIT(7)
+#define LAB_SW_HIGH_PSRR_REQ BIT(0)
+
+/* REG_LAB_VPH_ENVELOP_CTL */
+#define LAB_VREF_HIGH_PSRR_SEL_MASK GENMASK(7, 6)
+#define LAB_SEL_HW_HIGH_PSRR_SRC_MASK GENMASK(1, 0)
+#define LAB_SEL_HW_HIGH_PSRR_SRC_SHIFT 6
+
+/* IBB register offset definitions */
+#define REG_IBB_REVISION4 0x03
+#define REG_IBB_STATUS1 0x08
+#define REG_IBB_VOLTAGE 0x41
+#define REG_IBB_RING_SUPPRESSION_CTL 0x42
+#define REG_IBB_LCD_AMOLED_SEL 0x44
+#define REG_IBB_MODULE_RDY 0x45
+#define REG_IBB_ENABLE_CTL 0x46
+#define REG_IBB_PD_CTL 0x47
+#define REG_IBB_CLK_DIV 0x48
+#define REG_IBB_CURRENT_LIMIT 0x4B
+#define REG_IBB_PS_CTL 0x50
+#define REG_IBB_RDSON_MNGMNT 0x53
+#define REG_IBB_NONOVERLAP_TIME_1 0x56
+#define REG_IBB_NONOVERLAP_TIME_2 0x57
+#define REG_IBB_PWRUP_PWRDN_CTL_1 0x58
+#define REG_IBB_PWRUP_PWRDN_CTL_2 0x59
+#define REG_IBB_SOFT_START_CTL 0x5F
+#define REG_IBB_SWIRE_CTL 0x5A
+#define REG_IBB_OUTPUT_SLEW_CTL 0x5D
+#define REG_IBB_SPARE_CTL 0x60
+#define REG_IBB_NLIMIT_DAC 0x61
+
+/* IBB registers for PM660A */
+#define REG_IBB_DEFAULT_VOLTAGE 0x40
+#define REG_IBB_FLOAT_CTL 0x43
+#define REG_IBB_VREG_OK_CTL 0x55
+#define REG_IBB_VOUT_MIN_MAGNITUDE 0x5C
+#define REG_IBB_PFM_CTL 0x62
+#define REG_IBB_SMART_PS_CTL 0x65
+#define REG_IBB_ADAPT_DEAD_TIME 0x67
+
+/* IBB register bits definition */
+
+/* REG_IBB_STATUS1 */
+#define IBB_STATUS1_VREG_OK_MASK BIT(7)
+#define IBB_STATUS1_VREG_OK BIT(7)
+
+/* REG_IBB_VOLTAGE */
+#define IBB_VOLTAGE_OVERRIDE_EN BIT(7)
+#define IBB_VOLTAGE_SET_MASK GENMASK(5, 0)
+
+/* REG_IBB_CLK_DIV */
+#define IBB_CLK_DIV_OVERRIDE_EN BIT(7)
+#define IBB_CLK_DIV_MASK GENMASK(3, 0)
+
+/* REG_IBB_RING_SUPPRESSION_CTL */
+#define IBB_RING_SUPPRESSION_CTL_EN BIT(7)
+
+/* REG_IBB_FLOAT_CTL */
+#define IBB_FLOAT_EN BIT(0)
+#define IBB_SMART_FLOAT_EN BIT(7)
+
+/* REG_IBB_MIN_MAGNITUDE */
+#define IBB_MIN_VOLTAGE_0P8_V BIT(3)
+
+/* REG_IBB_MODULE_RDY */
+#define IBB_MODULE_RDY_EN BIT(7)
+
+/* REG_IBB_ENABLE_CTL */
+#define IBB_ENABLE_CTL_MASK (BIT(7) | BIT(6))
+#define IBB_ENABLE_CTL_SWIRE_RDY BIT(6)
+#define IBB_ENABLE_CTL_MODULE_EN BIT(7)
+
+/* REG_IBB_PD_CTL */
+#define IBB_PD_CTL_HALF_STRENGTH BIT(0)
+#define IBB_PD_CTL_STRENGTH_MASK BIT(0)
+#define IBB_PD_CTL_EN BIT(7)
+#define IBB_SWIRE_PD_UPD BIT(1)
+#define IBB_PD_CTL_EN_MASK BIT(7)
+
+/* REG_IBB_CURRENT_LIMIT */
+#define IBB_CURRENT_LIMIT_MASK GENMASK(4, 0)
+#define IBB_CURRENT_LIMIT_DEBOUNCE_SHIFT 5
+#define IBB_CURRENT_LIMIT_DEBOUNCE_MASK GENMASK(6, 5)
+#define IBB_CURRENT_LIMIT_EN BIT(7)
+#define IBB_ILIMIT_COUNT_CYC8 0
+#define IBB_CURRENT_MAX_500MA 0xA
+
+/* REG_IBB_PS_CTL */
+#define IBB_PS_CTL_EN 0x85
+
+/* REG_IBB_SMART_PS_CTL */
+#define IBB_SMART_PS_CTL_EN BIT(7)
+#define IBB_NUM_SWIRE_PULSE_WAIT 0x5
+
+/* REG_IBB_OUTPUT_SLEW_CTL */
+#define IBB_SLEW_CTL_EN BIT(7)
+#define IBB_SLEW_RATE_SPEED_FAST_EN BIT(6)
+#define IBB_SLEW_RATE_TRANS_TIME_FAST_SHIFT 3
+#define IBB_SLEW_RATE_TRANS_TIME_FAST_MASK GENMASK(5, 3)
+#define IBB_SLEW_RATE_TRANS_TIME_SLOW_MASK GENMASK(2, 0)
+
+/* REG_IBB_VREG_OK_CTL */
+#define IBB_VREG_OK_EN_OVERLOAD_BLANK BIT(7)
+#define IBB_VREG_OK_OVERLOAD_DEB_SHIFT 5
+#define IBB_VREG_OK_OVERLOAD_DEB_MASK GENMASK(6, 5)
+
+/* REG_IBB_RDSON_MNGMNT */
+#define IBB_NFET_SLEW_EN BIT(7)
+#define IBB_PFET_SLEW_EN BIT(6)
+#define IBB_OVERRIDE_NFET_SW_SIZE BIT(5)
+#define IBB_OVERRIDE_PFET_SW_SIZE BIT(2)
+#define IBB_NFET_SW_SIZE_MASK GENMASK(3, 2)
+#define IBB_PFET_SW_SIZE_MASK GENMASK(1, 0)
+
+/* REG_IBB_NONOVERLAP_TIME_1 */
+#define IBB_OVERRIDE_NONOVERLAP BIT(6)
+#define IBB_NONOVERLAP_NFET_MASK GENMASK(2, 0)
+#define IBB_NFET_GATE_DELAY_2 0x3
+
+/* REG_IBB_NONOVERLAP_TIME_2 */
+#define IBB_N2P_MUX_SEL BIT(0)
+
+/* REG_IBB_SOFT_START_CTL */
+#define IBB_SOFT_START_CHARGING_RESISTOR_16K 0x3
+
+/* REG_IBB_SPARE_CTL */
+#define IBB_BYPASS_PWRDN_DLY2_BIT BIT(5)
+#define IBB_POFF_CTL_MASK BIT(4)
+#define IBB_FASTER_PFET_OFF BIT(4)
+#define IBB_FAST_STARTUP BIT(3)
+
+/* REG_IBB_SWIRE_CTL */
+#define IBB_SWIRE_VOUT_UPD_EN BIT(6)
+#define IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_MASK GENMASK(5, 0)
+#define MAX_OUTPUT_EDGE_VOLTAGE_MV 6300
+#define MAX_OUTPUT_PULSE_VOLTAGE_MV 7700
+#define MIN_OUTPUT_PULSE_VOLTAGE_MV 1400
+#define OUTPUT_VOLTAGE_STEP_MV 100
+
+/* REG_IBB_NLIMIT_DAC */
+#define IBB_DEFAULT_NLIMIT_DAC 0x5
+
+/* REG_IBB_PFM_CTL */
+#define IBB_PFM_ENABLE BIT(7)
+#define IBB_PFM_PEAK_CURRENT_BIT_SHIFT 1
+#define IBB_PFM_PEAK_CURRENT_MASK GENMASK(3, 1)
+#define IBB_PFM_HYSTERESIS_BIT_SHIFT 4
+#define IBB_PFM_HYSTERESIS_MASK GENMASK(5, 4)
+
+/* REG_IBB_PWRUP_PWRDN_CTL_1 */
+#define IBB_PWRUP_PWRDN_CTL_1_DLY1_BITS 2
+#define IBB_PWRUP_PWRDN_CTL_1_DLY1_MASK GENMASK(5, 4)
+#define IBB_PWRUP_PWRDN_CTL_1_DLY1_SHIFT 4
+#define IBB_PWRUP_PWRDN_CTL_1_EN_DLY2 BIT(3)
+#define IBB_PWRUP_PWRDN_CTL_1_DLY2_MASK GENMASK(1, 0)
+#define IBB_PWRUP_PWRDN_CTL_1_LAB_VREG_OK BIT(7)
+#define IBB_PWRUP_PWRDN_CTL_1_EN_DLY1 BIT(6)
+#define PWRUP_PWRDN_CTL_1_DISCHARGE_EN BIT(2)
+
+/* REG_IBB_PWRUP_PWRDN_CTL_2 */
+#define IBB_DIS_DLY_MASK GENMASK(1, 0)
+#define IBB_WAIT_MBG_OK BIT(2)
+
+/* Constants */
+#define SWIRE_DEFAULT_2ND_CMD_DLY_MS 20
+#define SWIRE_DEFAULT_IBB_PS_ENABLE_DLY_MS 200
+#define IBB_HW_DEFAULT_SLEW_RATE 12000
+
+/**
+ * enum qpnp_labibb_mode - working mode of LAB/IBB regulators
+ * %QPNP_LABIBB_LCD_MODE: configure LAB and IBB regulators
+ * together to provide power supply for LCD
+ * %QPNP_LABIBB_AMOLED_MODE: configure LAB and IBB regulators
+ * together to provide power supply for AMOLED
+ * %QPNP_LABIBB_MAX_MODE max number of configureable modes
+ * supported by qpnp_labibb_regulator
+ */
+enum qpnp_labibb_mode {
+ QPNP_LABIBB_LCD_MODE,
+ QPNP_LABIBB_AMOLED_MODE,
+ QPNP_LABIBB_MAX_MODE,
+};
+
+/**
+ * IBB_SW_CONTROL_EN: Specifies IBB is enabled through software.
+ * IBB_SW_CONTROL_DIS: Specifies IBB is disabled through software.
+ * IBB_HW_CONTROL: Specifies IBB is controlled through SWIRE (hardware).
+ */
+enum ibb_mode {
+ IBB_SW_CONTROL_EN,
+ IBB_SW_CONTROL_DIS,
+ IBB_HW_CONTROL,
+ IBB_HW_SW_CONTROL,
+};
+
+static const int ibb_dischg_res_table[] = {
+ 300,
+ 64,
+ 32,
+ 16,
+};
+
+static const int ibb_pwrup_dly_table[] = {
+ 1000,
+ 2000,
+ 4000,
+ 8000,
+};
+
+static const int ibb_pwrdn_dly_table[] = {
+ 1000,
+ 2000,
+ 4000,
+ 8000,
+};
+
+static const int lab_clk_div_table[] = {
+ 3200,
+ 2740,
+ 2400,
+ 2130,
+ 1920,
+ 1750,
+ 1600,
+ 1480,
+ 1370,
+ 1280,
+ 1200,
+ 1130,
+ 1070,
+ 1010,
+ 960,
+ 910,
+};
+
+static const int ibb_clk_div_table[] = {
+ 3200,
+ 2740,
+ 2400,
+ 2130,
+ 1920,
+ 1750,
+ 1600,
+ 1480,
+ 1370,
+ 1280,
+ 1200,
+ 1130,
+ 1070,
+ 1010,
+ 960,
+ 910,
+};
+
+static const int lab_current_limit_table[] = {
+ 200,
+ 400,
+ 600,
+ 800,
+ 1000,
+ 1200,
+ 1400,
+ 1600,
+};
+
+static const char * const lab_current_sense_table[] = {
+ "0.5x",
+ "1x",
+ "1.5x",
+ "2x"
+};
+
+static const int ibb_current_limit_table[] = {
+ 0,
+ 50,
+ 100,
+ 150,
+ 200,
+ 250,
+ 300,
+ 350,
+ 400,
+ 450,
+ 500,
+ 550,
+ 600,
+ 650,
+ 700,
+ 750,
+ 800,
+ 850,
+ 900,
+ 950,
+ 1000,
+ 1050,
+ 1100,
+ 1150,
+ 1200,
+ 1250,
+ 1300,
+ 1350,
+ 1400,
+ 1450,
+ 1500,
+ 1550,
+};
+
+static const int ibb_output_slew_ctl_table[] = {
+ 100,
+ 200,
+ 500,
+ 1000,
+ 2000,
+ 10000,
+ 12000,
+ 15000
+};
+
+static const int ibb_debounce_table[] = {
+ 8,
+ 16,
+ 32,
+ 64,
+};
+
+static const int ibb_overload_debounce_table[] = {
+ 1,
+ 2,
+ 4,
+ 8
+};
+
+static const int ibb_vreg_ok_deb_table[] = {
+ 4,
+ 8,
+ 16,
+ 32
+};
+
+static const int lab_ps_thresh_table_v1[] = {
+ 20,
+ 30,
+ 40,
+ 50,
+};
+
+static const int lab_ps_thresh_table_v2[] = {
+ 50,
+ 60,
+ 70,
+ 80,
+};
+
+static const int lab_soft_start_table[] = {
+ 200,
+ 400,
+ 600,
+ 800,
+};
+
+static const int lab_rdson_nfet_table[] = {
+ 25,
+ 50,
+ 75,
+ 100,
+};
+
+static const int lab_rdson_pfet_table[] = {
+ 25,
+ 50,
+ 75,
+ 100,
+};
+
+static const int lab_max_precharge_table[] = {
+ 200,
+ 300,
+ 400,
+ 500,
+};
+
+static const int ibb_pfm_peak_curr_table[] = {
+ 150,
+ 200,
+ 250,
+ 300,
+ 350,
+ 400,
+ 450,
+ 500
+};
+
+static const int ibb_pfm_hysteresis_table[] = {
+ 0,
+ 25,
+ 50,
+ 0
+};
+
+static const int lab_vref_high_psrr_table[] = {
+ 350,
+ 400,
+ 450,
+ 500
+};
+
+struct lab_regulator {
+ struct regulator_desc rdesc;
+ struct regulator_dev *rdev;
+ struct mutex lab_mutex;
+
+ int lab_vreg_ok_irq;
+ int curr_volt;
+ int min_volt;
+
+ int step_size;
+ int slew_rate;
+ int soft_start;
+
+ int vreg_enabled;
+};
+
+struct ibb_regulator {
+ struct regulator_desc rdesc;
+ struct regulator_dev *rdev;
+ struct mutex ibb_mutex;
+
+ int curr_volt;
+ int min_volt;
+
+ int step_size;
+ int slew_rate;
+ int soft_start;
+
+ u32 pwrup_dly;
+ u32 pwrdn_dly;
+
+ int vreg_enabled;
+ int num_swire_trans;
+};
+
+struct qpnp_labibb {
+ struct device *dev;
+ struct platform_device *pdev;
+ struct regmap *regmap;
+ struct pmic_revid_data *pmic_rev_id;
+ u16 lab_base;
+ u16 ibb_base;
+ u8 lab_dig_major;
+ u8 ibb_dig_major;
+ struct lab_regulator lab_vreg;
+ struct ibb_regulator ibb_vreg;
+ const struct ibb_ver_ops *ibb_ver_ops;
+ const struct lab_ver_ops *lab_ver_ops;
+ struct mutex bus_mutex;
+ enum qpnp_labibb_mode mode;
+ bool standalone;
+ bool ttw_en;
+ bool in_ttw_mode;
+ bool ibb_settings_saved;
+ bool swire_control;
+ bool pbs_control;
+ bool ttw_force_lab_on;
+ bool skip_2nd_swire_cmd;
+ bool pfm_enable;
+ u32 swire_2nd_cmd_delay;
+ u32 swire_ibb_ps_enable_delay;
+};
+
+struct ibb_ver_ops {
+ int (*set_default_voltage)(struct qpnp_labibb *labibb,
+ bool use_default);
+ int (*set_voltage)(struct qpnp_labibb *labibb, int min_uV, int max_uV);
+ int (*sel_mode)(struct qpnp_labibb *labibb, bool is_ibb);
+ int (*get_mode)(struct qpnp_labibb *labibb);
+ int (*set_clk_div)(struct qpnp_labibb *labibb, u8 val);
+ int (*smart_ps_config)(struct qpnp_labibb *labibb, bool enable,
+ int num_swire_trans, int neg_curr_limit);
+ int (*soft_start_ctl)(struct qpnp_labibb *labibb,
+ struct device_node *of_node);
+ int (*voltage_at_one_pulse)(struct qpnp_labibb *labibb, u32 volt);
+};
+
+struct lab_ver_ops {
+ const char *ver_str;
+ int (*set_default_voltage)(struct qpnp_labibb *labibb,
+ bool default_pres);
+ int (*ps_ctl)(struct qpnp_labibb *labibb,
+ u32 thresh, bool enable);
+};
+
+enum ibb_settings_index {
+ IBB_PD_CTL = 0,
+ IBB_CURRENT_LIMIT,
+ IBB_RDSON_MNGMNT,
+ IBB_PWRUP_PWRDN_CTL_1,
+ IBB_PWRUP_PWRDN_CTL_2,
+ IBB_NLIMIT_DAC,
+ IBB_PS_CTL,
+ IBB_SOFT_START_CTL,
+ IBB_SETTINGS_MAX,
+};
+
+enum lab_settings_index {
+ LAB_SOFT_START_CTL = 0,
+ LAB_PS_CTL,
+ LAB_RDSON_MNGMNT,
+ LAB_SETTINGS_MAX,
+};
+
+struct settings {
+ u16 address;
+ u8 value;
+ bool sec_access;
+};
+
+#define SETTING(_id, _sec_access) \
+ [_id] = { \
+ .address = REG_##_id, \
+ .sec_access = _sec_access, \
+ }
+
+static struct settings ibb_settings[IBB_SETTINGS_MAX] = {
+ SETTING(IBB_PD_CTL, false),
+ SETTING(IBB_CURRENT_LIMIT, true),
+ SETTING(IBB_RDSON_MNGMNT, false),
+ SETTING(IBB_PWRUP_PWRDN_CTL_1, true),
+ SETTING(IBB_PWRUP_PWRDN_CTL_2, true),
+ SETTING(IBB_NLIMIT_DAC, false),
+ SETTING(IBB_PS_CTL, false),
+ SETTING(IBB_SOFT_START_CTL, false),
+};
+
+static struct settings lab_settings[LAB_SETTINGS_MAX] = {
+ SETTING(LAB_SOFT_START_CTL, false),
+ SETTING(LAB_PS_CTL, false),
+ SETTING(LAB_RDSON_MNGMNT, false),
+};
+
+static int
+qpnp_labibb_read(struct qpnp_labibb *labibb, u16 address,
+ u8 *val, int count)
+{
+ int rc = 0;
+ struct platform_device *pdev = labibb->pdev;
+
+ mutex_lock(&(labibb->bus_mutex));
+ rc = regmap_bulk_read(labibb->regmap, address, val, count);
+ if (rc < 0)
+ pr_err("SPMI read failed address=0x%02x sid=0x%02x rc=%d\n",
+ address, to_spmi_device(pdev->dev.parent)->usid, rc);
+
+ mutex_unlock(&(labibb->bus_mutex));
+ return rc;
+}
+
+static int
+qpnp_labibb_write(struct qpnp_labibb *labibb, u16 address,
+ u8 *val, int count)
+{
+ int rc = 0;
+ struct platform_device *pdev = labibb->pdev;
+
+ mutex_lock(&(labibb->bus_mutex));
+ if (address == 0) {
+ pr_err("address cannot be zero address=0x%02x sid=0x%02x rc=%d\n",
+ address, to_spmi_device(pdev->dev.parent)->usid, rc);
+ rc = -EINVAL;
+ goto error;
+ }
+
+ rc = regmap_bulk_write(labibb->regmap, address, val, count);
+ if (rc < 0)
+ pr_err("write failed address=0x%02x sid=0x%02x rc=%d\n",
+ address, to_spmi_device(pdev->dev.parent)->usid, rc);
+
+error:
+ mutex_unlock(&(labibb->bus_mutex));
+ return rc;
+}
+
+static int
+qpnp_labibb_masked_write(struct qpnp_labibb *labibb, u16 address,
+ u8 mask, u8 val)
+{
+ int rc = 0;
+ struct platform_device *pdev = labibb->pdev;
+
+ mutex_lock(&(labibb->bus_mutex));
+ if (address == 0) {
+ pr_err("address cannot be zero address=0x%02x sid=0x%02x\n",
+ address, to_spmi_device(pdev->dev.parent)->usid);
+ rc = -EINVAL;
+ goto error;
+ }
+
+ rc = regmap_update_bits(labibb->regmap, address, mask, val);
+ if (rc < 0)
+ pr_err("spmi write failed: addr=%03X, rc=%d\n", address, rc);
+
+error:
+ mutex_unlock(&(labibb->bus_mutex));
+ return rc;
+}
+
+static int qpnp_labibb_sec_write(struct qpnp_labibb *labibb, u16 base,
+ u8 offset, u8 val)
+{
+ int rc = 0;
+ u8 sec_val = REG_LAB_IBB_SEC_UNLOCK_CODE;
+ struct platform_device *pdev = labibb->pdev;
+
+ mutex_lock(&(labibb->bus_mutex));
+ if (base == 0) {
+ pr_err("base cannot be zero base=0x%02x sid=0x%02x\n",
+ base, to_spmi_device(pdev->dev.parent)->usid);
+ rc = -EINVAL;
+ goto error;
+ }
+
+ rc = regmap_write(labibb->regmap, base + REG_LAB_IBB_SEC_ACCESS,
+ sec_val);
+ if (rc < 0) {
+ pr_err("register %x failed rc = %d\n",
+ base + REG_LAB_IBB_SEC_ACCESS, rc);
+ goto error;
+ }
+
+ rc = regmap_write(labibb->regmap, base + offset, val);
+ if (rc < 0)
+ pr_err("failed: addr=%03X, rc=%d\n",
+ base + offset, rc);
+
+error:
+ mutex_unlock(&(labibb->bus_mutex));
+ return rc;
+}
+
+static int qpnp_labibb_sec_masked_write(struct qpnp_labibb *labibb, u16 base,
+ u8 offset, u8 mask, u8 val)
+{
+ int rc = 0;
+ u8 sec_val = REG_LAB_IBB_SEC_UNLOCK_CODE;
+ struct platform_device *pdev = labibb->pdev;
+
+ mutex_lock(&(labibb->bus_mutex));
+ if (base == 0) {
+ pr_err("base cannot be zero base=0x%02x sid=0x%02x\n",
+ base, to_spmi_device(pdev->dev.parent)->usid);
+ rc = -EINVAL;
+ goto error;
+ }
+
+ rc = regmap_write(labibb->regmap, base + REG_LAB_IBB_SEC_ACCESS,
+ sec_val);
+ if (rc < 0) {
+ pr_err("register %x failed rc = %d\n",
+ base + REG_LAB_IBB_SEC_ACCESS, rc);
+ goto error;
+ }
+
+ rc = regmap_update_bits(labibb->regmap, base + offset, mask, val);
+ if (rc < 0)
+ pr_err("spmi write failed: addr=%03X, rc=%d\n", base, rc);
+
+error:
+ mutex_unlock(&(labibb->bus_mutex));
+ return rc;
+}
+
+static int qpnp_ibb_smart_ps_config_v1(struct qpnp_labibb *labibb, bool enable,
+ int num_swire_trans, int neg_curr_limit)
+{
+ return 0;
+}
+
+static int qpnp_ibb_smart_ps_config_v2(struct qpnp_labibb *labibb, bool enable,
+ int num_swire_trans, int neg_curr_limit)
+{
+ u8 val;
+ int rc = 0;
+
+ if (enable) {
+ val = IBB_NUM_SWIRE_PULSE_WAIT;
+ rc = qpnp_labibb_write(labibb,
+ labibb->ibb_base + REG_IBB_PS_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("write register %x failed rc = %d\n",
+ REG_IBB_PS_CTL, rc);
+ return rc;
+ }
+ }
+
+ val = enable ? IBB_SMART_PS_CTL_EN : IBB_NUM_SWIRE_PULSE_WAIT;
+ if (num_swire_trans)
+ val |= num_swire_trans;
+ else
+ val |= IBB_NUM_SWIRE_PULSE_WAIT;
+
+ rc = qpnp_labibb_write(labibb,
+ labibb->ibb_base + REG_IBB_SMART_PS_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("write register %x failed rc = %d\n",
+ REG_IBB_SMART_PS_CTL, rc);
+ return rc;
+ }
+
+ val = enable ? (neg_curr_limit ? neg_curr_limit :
+ IBB_DEFAULT_NLIMIT_DAC) : IBB_DEFAULT_NLIMIT_DAC;
+
+ rc = qpnp_labibb_write(labibb,
+ labibb->ibb_base + REG_IBB_NLIMIT_DAC, &val, 1);
+ if (rc < 0)
+ pr_err("write register %x failed rc = %d\n",
+ REG_IBB_NLIMIT_DAC, rc);
+
+ return rc;
+}
+
+static int qpnp_labibb_sel_mode_v1(struct qpnp_labibb *labibb, bool is_ibb)
+{
+ int rc = 0;
+ u8 val;
+ u16 base;
+
+ val = (labibb->mode == QPNP_LABIBB_LCD_MODE) ? REG_LAB_IBB_LCD_MODE :
+ REG_LAB_IBB_AMOLED_MODE;
+
+ base = is_ibb ? labibb->ibb_base : labibb->lab_base;
+
+ rc = qpnp_labibb_sec_write(labibb, base, REG_LAB_LCD_AMOLED_SEL,
+ val);
+ if (rc < 0)
+ pr_err("register %x failed rc = %d\n",
+ REG_LAB_LCD_AMOLED_SEL, rc);
+
+ return rc;
+}
+
+static int qpnp_labibb_sel_mode_v2(struct qpnp_labibb *labibb, bool is_ibb)
+{
+ return 0;
+}
+
+static int qpnp_ibb_get_mode_v1(struct qpnp_labibb *labibb)
+{
+ int rc = 0;
+ u8 val;
+
+ rc = qpnp_labibb_read(labibb, labibb->ibb_base + REG_IBB_LCD_AMOLED_SEL,
+ &val, 1);
+ if (rc < 0)
+ return rc;
+
+ if (val == REG_LAB_IBB_AMOLED_MODE)
+ labibb->mode = QPNP_LABIBB_AMOLED_MODE;
+ else
+ labibb->mode = QPNP_LABIBB_LCD_MODE;
+
+ return 0;
+}
+
+static int qpnp_ibb_get_mode_v2(struct qpnp_labibb *labibb)
+{
+ labibb->mode = QPNP_LABIBB_AMOLED_MODE;
+
+ return 0;
+}
+
+static int qpnp_ibb_set_clk_div_v1(struct qpnp_labibb *labibb, u8 val)
+{
+ int rc = 0;
+
+ rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_CLK_DIV,
+ &val, 1);
+
+ return rc;
+}
+
+static int qpnp_ibb_set_clk_div_v2(struct qpnp_labibb *labibb, u8 val)
+{
+ int rc = 0;
+
+ val |= IBB_CLK_DIV_OVERRIDE_EN;
+ rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base +
+ REG_IBB_CLK_DIV, IBB_CLK_DIV_MASK |
+ IBB_CLK_DIV_OVERRIDE_EN, val);
+
+ return rc;
+}
+
+static int qpnp_ibb_soft_start_ctl_v1(struct qpnp_labibb *labibb,
+ struct device_node *of_node)
+{
+ int rc = 0;
+ u8 val;
+ u32 tmp;
+
+ rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-soft-start",
+ &(labibb->ibb_vreg.soft_start));
+ if (rc < 0) {
+ pr_err("qcom,qpnp-ibb-soft-start is missing, rc = %d\n",
+ rc);
+ return rc;
+ }
+
+ rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-discharge-resistor",
+ &tmp);
+ if (!rc) {
+ for (val = 0; val < ARRAY_SIZE(ibb_dischg_res_table); val++) {
+ if (ibb_dischg_res_table[val] == tmp)
+ break;
+ }
+
+ if (val == ARRAY_SIZE(ibb_dischg_res_table)) {
+ pr_err("Invalid value in qcom,qpnp-ibb-discharge-resistor\n");
+ return -EINVAL;
+ }
+
+ rc = qpnp_labibb_write(labibb, labibb->ibb_base +
+ REG_IBB_SOFT_START_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ REG_IBB_SOFT_START_CTL, rc);
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+static int qpnp_ibb_soft_start_ctl_v2(struct qpnp_labibb *labibb,
+ struct device_node *of_node)
+{
+ return 0;
+}
+
+static int qpnp_ibb_vreg_ok_ctl(struct qpnp_labibb *labibb,
+ struct device_node *of_node)
+{
+ u8 val = 0;
+ int rc = 0, i = 0;
+ u32 tmp;
+
+ if (labibb->pmic_rev_id->pmic_subtype != PM660L_SUBTYPE)
+ return rc;
+
+ val |= IBB_VREG_OK_EN_OVERLOAD_BLANK;
+
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-ibb-overload-debounce", &tmp);
+ if (rc < 0) {
+ pr_err("failed to read qcom,qpnp-ibb-overload-debounce rc=%d\n",
+ rc);
+ return rc;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(ibb_overload_debounce_table); i++)
+ if (ibb_overload_debounce_table[i] == tmp)
+ break;
+
+ if (i == ARRAY_SIZE(ibb_overload_debounce_table)) {
+ pr_err("Invalid value in qcom,qpnp-ibb-overload-debounce\n");
+ return -EINVAL;
+ }
+ val |= i << IBB_VREG_OK_OVERLOAD_DEB_SHIFT;
+
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-ibb-vreg-ok-debounce", &tmp);
+ if (rc < 0) {
+ pr_err("failed to read qcom,qpnp-ibb-vreg-ok-debounce rc=%d\n",
+ rc);
+ return rc;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(ibb_vreg_ok_deb_table); i++)
+ if (ibb_vreg_ok_deb_table[i] == tmp)
+ break;
+
+ if (i == ARRAY_SIZE(ibb_vreg_ok_deb_table)) {
+ pr_err("Invalid value in qcom,qpnp-ibb-vreg-ok-debounce\n");
+ return -EINVAL;
+ }
+ val |= i;
+
+ rc = qpnp_labibb_write(labibb, labibb->ibb_base +
+ REG_IBB_VREG_OK_CTL,
+ &val, 1);
+ if (rc < 0)
+ pr_err("write to register %x failed rc = %d\n",
+ REG_IBB_VREG_OK_CTL, rc);
+
+ return rc;
+}
+
+static int qpnp_ibb_set_default_voltage_v1(struct qpnp_labibb *labibb,
+ bool use_default)
+{
+ u8 val;
+ int rc = 0;
+
+ if (!use_default) {
+ if (labibb->ibb_vreg.curr_volt < labibb->ibb_vreg.min_volt) {
+ pr_err("qcom,qpnp-ibb-init-voltage %d is less than the the minimum voltage %d",
+ labibb->ibb_vreg.curr_volt, labibb->ibb_vreg.min_volt);
+ return -EINVAL;
+ }
+
+ val = DIV_ROUND_UP(labibb->ibb_vreg.curr_volt -
+ labibb->ibb_vreg.min_volt,
+ labibb->ibb_vreg.step_size);
+ if (val > IBB_VOLTAGE_SET_MASK) {
+ pr_err("qcom,qpnp-lab-init-voltage %d is larger than the max supported voltage %ld",
+ labibb->ibb_vreg.curr_volt,
+ labibb->ibb_vreg.min_volt +
+ labibb->ibb_vreg.step_size *
+ IBB_VOLTAGE_SET_MASK);
+ return -EINVAL;
+ }
+
+ labibb->ibb_vreg.curr_volt = val * labibb->ibb_vreg.step_size +
+ labibb->ibb_vreg.min_volt;
+ val |= IBB_VOLTAGE_OVERRIDE_EN;
+ } else {
+ val = 0;
+ }
+
+ rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base +
+ REG_IBB_VOLTAGE, IBB_VOLTAGE_SET_MASK |
+ IBB_VOLTAGE_OVERRIDE_EN, val);
+ if (rc < 0)
+ pr_err("write to register %x failed rc = %d\n", REG_IBB_VOLTAGE,
+ rc);
+
+ return rc;
+}
+
+static int qpnp_ibb_set_default_voltage_v2(struct qpnp_labibb *labibb,
+ bool use_default)
+{
+ int rc = 0;
+ u8 val;
+
+ val = DIV_ROUND_UP(labibb->ibb_vreg.curr_volt,
+ labibb->ibb_vreg.step_size);
+ if (val > IBB_VOLTAGE_SET_MASK) {
+ pr_err("Invalid qcom,qpnp-ibb-init-voltage property %d",
+ labibb->ibb_vreg.curr_volt);
+ return -EINVAL;
+ }
+
+ labibb->ibb_vreg.curr_volt = val * labibb->ibb_vreg.step_size;
+
+ rc = qpnp_labibb_write(labibb, labibb->ibb_base +
+ REG_IBB_DEFAULT_VOLTAGE, &val, 1);
+ if (rc < 0)
+ pr_err("write to register %x failed rc = %d\n",
+ REG_IBB_DEFAULT_VOLTAGE, rc);
+
+ return rc;
+}
+
+static int qpnp_ibb_set_voltage_v1(struct qpnp_labibb *labibb,
+ int min_uV, int max_uV)
+{
+ int rc, new_uV;
+ u8 val;
+
+ if (min_uV < labibb->ibb_vreg.min_volt) {
+ pr_err("min_uV %d is less than min_volt %d", min_uV,
+ labibb->ibb_vreg.min_volt);
+ return -EINVAL;
+ }
+
+ val = DIV_ROUND_UP(min_uV - labibb->ibb_vreg.min_volt,
+ labibb->ibb_vreg.step_size);
+ new_uV = val * labibb->ibb_vreg.step_size + labibb->ibb_vreg.min_volt;
+
+ if (new_uV > max_uV) {
+ pr_err("unable to set voltage %d (min:%d max:%d)\n", new_uV,
+ min_uV, max_uV);
+ return -EINVAL;
+ }
+
+ rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base +
+ REG_IBB_VOLTAGE,
+ IBB_VOLTAGE_SET_MASK |
+ IBB_VOLTAGE_OVERRIDE_EN,
+ val | IBB_VOLTAGE_OVERRIDE_EN);
+
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n", REG_IBB_VOLTAGE,
+ rc);
+ return rc;
+ }
+
+ if (new_uV > labibb->ibb_vreg.curr_volt) {
+ val = DIV_ROUND_UP(new_uV - labibb->ibb_vreg.curr_volt,
+ labibb->ibb_vreg.step_size);
+ udelay(val * labibb->ibb_vreg.slew_rate);
+ }
+ labibb->ibb_vreg.curr_volt = new_uV;
+
+ return 0;
+}
+
+static int qpnp_ibb_set_voltage_v2(struct qpnp_labibb *labibb,
+ int min_uV, int max_uV)
+{
+ int rc, new_uV;
+ u8 val;
+
+ val = DIV_ROUND_UP(min_uV, labibb->ibb_vreg.step_size);
+ new_uV = val * labibb->ibb_vreg.step_size;
+
+ if (new_uV > max_uV) {
+ pr_err("unable to set voltage %d (min:%d max:%d)\n", new_uV,
+ min_uV, max_uV);
+ return -EINVAL;
+ }
+
+ rc = qpnp_labibb_write(labibb, labibb->ibb_base +
+ REG_IBB_VOLTAGE, &val, 1);
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n", REG_IBB_VOLTAGE,
+ rc);
+ return rc;
+ }
+
+ if (new_uV > labibb->ibb_vreg.curr_volt) {
+ val = DIV_ROUND_UP(new_uV - labibb->ibb_vreg.curr_volt,
+ labibb->ibb_vreg.step_size);
+ udelay(val * labibb->ibb_vreg.slew_rate);
+ }
+ labibb->ibb_vreg.curr_volt = new_uV;
+
+ return 0;
+}
+
+static int qpnp_ibb_output_voltage_at_one_pulse_v1(struct qpnp_labibb *labibb,
+ u32 volt)
+{
+ int rc = 0;
+ u8 val;
+
+ /*
+ * Set the output voltage 100mV lower as the IBB HW module
+ * counts one pulse less in SWIRE mode.
+ */
+ val = DIV_ROUND_UP((volt - MIN_OUTPUT_PULSE_VOLTAGE_MV),
+ OUTPUT_VOLTAGE_STEP_MV) - 1;
+ rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base +
+ REG_IBB_SWIRE_CTL,
+ IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_MASK,
+ val);
+ if (rc < 0)
+ pr_err("write register %x failed rc = %d\n",
+ REG_IBB_SWIRE_CTL, rc);
+
+ return rc;
+}
+
+static int qpnp_ibb_output_voltage_at_one_pulse_v2(struct qpnp_labibb *labibb,
+ u32 volt)
+{
+ int rc = 0;
+ u8 val;
+
+ val = DIV_ROUND_UP(volt, OUTPUT_VOLTAGE_STEP_MV);
+
+ rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base +
+ REG_IBB_SWIRE_CTL,
+ IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_MASK,
+ val);
+ if (rc < 0)
+ pr_err("qpnp_labiibb_write register %x failed rc = %d\n",
+ REG_IBB_SWIRE_CTL, rc);
+
+ return rc;
+}
+
+static const struct ibb_ver_ops ibb_ops_v1 = {
+ .set_default_voltage = qpnp_ibb_set_default_voltage_v1,
+ .set_voltage = qpnp_ibb_set_voltage_v1,
+ .sel_mode = qpnp_labibb_sel_mode_v1,
+ .get_mode = qpnp_ibb_get_mode_v1,
+ .set_clk_div = qpnp_ibb_set_clk_div_v1,
+ .smart_ps_config = qpnp_ibb_smart_ps_config_v1,
+ .soft_start_ctl = qpnp_ibb_soft_start_ctl_v1,
+ .voltage_at_one_pulse = qpnp_ibb_output_voltage_at_one_pulse_v1,
+};
+
+static const struct ibb_ver_ops ibb_ops_v2 = {
+ .set_default_voltage = qpnp_ibb_set_default_voltage_v2,
+ .set_voltage = qpnp_ibb_set_voltage_v2,
+ .sel_mode = qpnp_labibb_sel_mode_v2,
+ .get_mode = qpnp_ibb_get_mode_v2,
+ .set_clk_div = qpnp_ibb_set_clk_div_v2,
+ .smart_ps_config = qpnp_ibb_smart_ps_config_v2,
+ .soft_start_ctl = qpnp_ibb_soft_start_ctl_v2,
+ .voltage_at_one_pulse = qpnp_ibb_output_voltage_at_one_pulse_v2,
+};
+
+static int qpnp_lab_set_default_voltage_v1(struct qpnp_labibb *labibb,
+ bool default_pres)
+{
+ u8 val;
+ int rc = 0;
+
+ if (!default_pres) {
+ if (labibb->lab_vreg.curr_volt < labibb->lab_vreg.min_volt) {
+ pr_err("qcom,qpnp-lab-init-voltage %d is less than the the minimum voltage %d",
+ labibb->lab_vreg.curr_volt,
+ labibb->lab_vreg.min_volt);
+ return -EINVAL;
+ }
+
+ val = DIV_ROUND_UP(labibb->lab_vreg.curr_volt -
+ labibb->lab_vreg.min_volt,
+ labibb->lab_vreg.step_size);
+ if (val > LAB_VOLTAGE_SET_MASK) {
+ pr_err("qcom,qpnp-lab-init-voltage %d is larger than the max supported voltage %ld",
+ labibb->lab_vreg.curr_volt,
+ labibb->lab_vreg.min_volt +
+ labibb->lab_vreg.step_size *
+ LAB_VOLTAGE_SET_MASK);
+ return -EINVAL;
+ }
+
+ labibb->lab_vreg.curr_volt = val * labibb->lab_vreg.step_size +
+ labibb->lab_vreg.min_volt;
+ val |= LAB_VOLTAGE_OVERRIDE_EN;
+
+ } else {
+ val = 0;
+ }
+
+ rc = qpnp_labibb_masked_write(labibb, labibb->lab_base +
+ REG_LAB_VOLTAGE, LAB_VOLTAGE_SET_MASK |
+ LAB_VOLTAGE_OVERRIDE_EN, val);
+
+ if (rc < 0)
+ pr_err("write to register %x failed rc = %d\n", REG_LAB_VOLTAGE,
+ rc);
+
+ return rc;
+}
+
+static int qpnp_lab_set_default_voltage_v2(struct qpnp_labibb *labibb,
+ bool default_pres)
+{
+ int rc = 0;
+ u8 val;
+
+ val = DIV_ROUND_UP((labibb->lab_vreg.curr_volt
+ - labibb->lab_vreg.min_volt), labibb->lab_vreg.step_size);
+
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_VOUT_DEFAULT, &val, 1);
+ if (rc < 0)
+ pr_err("write to register %x failed rc = %d\n",
+ REG_LAB_VOUT_DEFAULT, rc);
+
+ return rc;
+}
+
+static int qpnp_lab_ps_ctl_v1(struct qpnp_labibb *labibb,
+ u32 thresh, bool enable)
+{
+ int rc = 0;
+ u8 val;
+
+ if (enable) {
+ for (val = 0; val < ARRAY_SIZE(lab_ps_thresh_table_v1); val++)
+ if (lab_ps_thresh_table_v1[val] == thresh)
+ break;
+
+ if (val == ARRAY_SIZE(lab_ps_thresh_table_v1)) {
+ pr_err("Invalid value in qcom,qpnp-lab-ps-threshold\n");
+ return -EINVAL;
+ }
+
+ val |= LAB_PS_CTL_EN;
+ } else {
+ val = 0;
+ }
+
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_PS_CTL, &val, 1);
+
+ if (rc < 0)
+ pr_err("write register %x failed rc = %d\n",
+ REG_LAB_PS_CTL, rc);
+
+ return rc;
+}
+
+static int qpnp_lab_ps_ctl_v2(struct qpnp_labibb *labibb,
+ u32 thresh, bool enable)
+{
+ int rc = 0;
+ u8 val;
+
+ if (enable) {
+ for (val = 0; val < ARRAY_SIZE(lab_ps_thresh_table_v2); val++)
+ if (lab_ps_thresh_table_v2[val] == thresh)
+ break;
+
+ if (val == ARRAY_SIZE(lab_ps_thresh_table_v2)) {
+ pr_err("Invalid value in qcom,qpnp-lab-ps-threshold\n");
+ return -EINVAL;
+ }
+
+ val |= LAB_PS_CTL_EN;
+ } else {
+ val = 0;
+ }
+
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_PS_CTL, &val, 1);
+
+ if (rc < 0)
+ pr_err("write register %x failed rc = %d\n",
+ REG_LAB_PS_CTL, rc);
+
+ return rc;
+}
+
+static const struct lab_ver_ops lab_ops_v1 = {
+ .set_default_voltage = qpnp_lab_set_default_voltage_v1,
+ .ps_ctl = qpnp_lab_ps_ctl_v1,
+};
+
+static const struct lab_ver_ops lab_ops_v2 = {
+ .set_default_voltage = qpnp_lab_set_default_voltage_v2,
+ .ps_ctl = qpnp_lab_ps_ctl_v2,
+};
+
+static int qpnp_labibb_get_matching_idx(const char *val)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(lab_current_sense_table); i++)
+ if (!strcmp(lab_current_sense_table[i], val))
+ return i;
+
+ return -EINVAL;
+}
+
+static int qpnp_ibb_set_mode(struct qpnp_labibb *labibb, enum ibb_mode mode)
+{
+ int rc;
+ u8 val;
+
+ if (mode == IBB_SW_CONTROL_EN)
+ val = IBB_ENABLE_CTL_MODULE_EN;
+ else if (mode == IBB_HW_CONTROL)
+ val = IBB_ENABLE_CTL_SWIRE_RDY;
+ else if (mode == IBB_HW_SW_CONTROL)
+ val = IBB_ENABLE_CTL_MODULE_EN | IBB_ENABLE_CTL_SWIRE_RDY;
+ else if (mode == IBB_SW_CONTROL_DIS)
+ val = 0;
+ else
+ return -EINVAL;
+
+ rc = qpnp_labibb_masked_write(labibb,
+ labibb->ibb_base + REG_IBB_ENABLE_CTL,
+ IBB_ENABLE_CTL_MASK, val);
+ if (rc < 0)
+ pr_err("Unable to configure IBB_ENABLE_CTL rc=%d\n", rc);
+
+ return rc;
+}
+
+static int qpnp_ibb_ps_config(struct qpnp_labibb *labibb, bool enable)
+{
+ u8 val;
+ int rc;
+
+ val = enable ? IBB_PS_CTL_EN : IBB_NUM_SWIRE_PULSE_WAIT;
+ rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_PS_CTL,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("write register %x failed rc = %d\n",
+ REG_IBB_PS_CTL, rc);
+ return rc;
+ }
+
+ val = enable ? 0 : IBB_DEFAULT_NLIMIT_DAC;
+ rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_NLIMIT_DAC,
+ &val, 1);
+ if (rc < 0)
+ pr_err("write register %x failed rc = %d\n",
+ REG_IBB_NLIMIT_DAC, rc);
+ return rc;
+}
+
+static int qpnp_lab_dt_init(struct qpnp_labibb *labibb,
+ struct device_node *of_node)
+{
+ int rc = 0;
+ u8 i, val, mask;
+ u32 tmp;
+
+ /*
+ * Do not configure LCD_AMOLED_SEL for pmi8998 as it will be done by
+ * GPIO selector.
+ */
+ if (labibb->pmic_rev_id->pmic_subtype != PMI8998_SUBTYPE) {
+ rc = labibb->ibb_ver_ops->sel_mode(labibb, 0);
+ if (rc < 0)
+ return rc;
+ }
+
+ val = 0;
+ if (of_property_read_bool(of_node, "qcom,qpnp-lab-full-pull-down"))
+ val |= LAB_PD_CTL_STRONG_PULL;
+
+ if (!of_property_read_bool(of_node, "qcom,qpnp-lab-pull-down-enable"))
+ val |= LAB_PD_CTL_DISABLE_PD;
+
+ mask = LAB_PD_CTL_EN_MASK | LAB_PD_CTL_STRENGTH_MASK;
+ rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + REG_LAB_PD_CTL,
+ mask, val);
+
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ REG_LAB_PD_CTL, rc);
+ return rc;
+ }
+
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-lab-switching-clock-frequency", &tmp);
+ if (!rc) {
+ for (val = 0; val < ARRAY_SIZE(lab_clk_div_table); val++)
+ if (lab_clk_div_table[val] == tmp)
+ break;
+
+ if (val == ARRAY_SIZE(lab_clk_div_table)) {
+ pr_err("Invalid value in qpnp-lab-switching-clock-frequency\n");
+ return -EINVAL;
+ }
+
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_CLK_DIV, &val, 1);
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ REG_LAB_CLK_DIV, rc);
+ return rc;
+ }
+ }
+
+ if (of_property_read_bool(of_node,
+ "qcom,qpnp-lab-limit-max-current-enable")) {
+ val = LAB_CURRENT_LIMIT_EN_BIT;
+
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-lab-limit-maximum-current", &tmp);
+
+ if (rc < 0) {
+ pr_err("get qcom,qpnp-lab-limit-maximum-current failed rc = %d\n",
+ rc);
+ return rc;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(lab_current_limit_table); i++)
+ if (lab_current_limit_table[i] == tmp)
+ break;
+
+ if (i == ARRAY_SIZE(lab_current_limit_table)) {
+ pr_err("Invalid value in qcom,qpnp-lab-limit-maximum-current\n");
+ return -EINVAL;
+ }
+
+ val |= i;
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_CURRENT_LIMIT, &val, 1);
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ REG_LAB_CURRENT_LIMIT, rc);
+ return rc;
+ }
+ }
+
+ if (of_property_read_bool(of_node,
+ "qcom,qpnp-lab-ring-suppression-enable")) {
+ val = LAB_RING_SUPPRESSION_CTL_EN;
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_RING_SUPPRESSION_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ REG_LAB_RING_SUPPRESSION_CTL, rc);
+ return rc;
+ }
+ }
+
+ if (of_property_read_bool(of_node, "qcom,qpnp-lab-ps-enable")) {
+
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-lab-ps-threshold", &tmp);
+
+ if (rc < 0) {
+ pr_err("get qcom,qpnp-lab-ps-threshold failed rc = %d\n",
+ rc);
+ return rc;
+ }
+ rc = labibb->lab_ver_ops->ps_ctl(labibb, tmp, true);
+ if (rc < 0)
+ return rc;
+ } else {
+ rc = labibb->lab_ver_ops->ps_ctl(labibb, tmp, false);
+ if (rc < 0)
+ return rc;
+ }
+
+ val = 0;
+ mask = 0;
+ rc = of_property_read_u32(of_node, "qcom,qpnp-lab-pfet-size", &tmp);
+ if (!rc) {
+ for (val = 0; val < ARRAY_SIZE(lab_rdson_pfet_table); val++)
+ if (tmp == lab_rdson_pfet_table[val])
+ break;
+
+ if (val == ARRAY_SIZE(lab_rdson_pfet_table)) {
+ pr_err("Invalid value in qcom,qpnp-lab-pfet-size\n");
+ return -EINVAL;
+ }
+ val |= LAB_RDSON_MNGMNT_PFET_SLEW_EN;
+ mask |= LAB_RDSON_MNGMNT_PFET_MASK |
+ LAB_RDSON_MNGMNT_PFET_SLEW_EN;
+ }
+
+ rc = of_property_read_u32(of_node, "qcom,qpnp-lab-nfet-size",
+ &tmp);
+ if (!rc) {
+ for (i = 0; i < ARRAY_SIZE(lab_rdson_nfet_table); i++)
+ if (tmp == lab_rdson_nfet_table[i])
+ break;
+
+ if (i == ARRAY_SIZE(lab_rdson_nfet_table)) {
+ pr_err("Invalid value in qcom,qpnp-lab-nfet-size\n");
+ return -EINVAL;
+ }
+
+ val |= i << LAB_RDSON_MNGMNT_NFET_SHIFT;
+ val |= LAB_RDSON_MNGMNT_NFET_SLEW_EN;
+ mask |= LAB_RDSON_MNGMNT_NFET_MASK |
+ LAB_RDSON_MNGMNT_NFET_SLEW_EN;
+ }
+
+ rc = qpnp_labibb_masked_write(labibb, labibb->lab_base +
+ REG_LAB_RDSON_MNGMNT, mask, val);
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ REG_LAB_RDSON_MNGMNT, rc);
+ return rc;
+ }
+
+ rc = of_property_read_u32(of_node, "qcom,qpnp-lab-init-voltage",
+ &(labibb->lab_vreg.curr_volt));
+ if (rc < 0) {
+ pr_err("get qcom,qpnp-lab-init-voltage failed, rc = %d\n",
+ rc);
+ return rc;
+ }
+
+ if (of_property_read_bool(of_node,
+ "qcom,qpnp-lab-use-default-voltage"))
+ rc = labibb->lab_ver_ops->set_default_voltage(labibb, true);
+ else
+ rc = labibb->lab_ver_ops->set_default_voltage(labibb, false);
+
+ if (rc < 0)
+ return rc;
+
+ if (of_property_read_bool(of_node,
+ "qcom,qpnp-lab-enable-sw-high-psrr")) {
+ val = LAB_EN_SW_HIGH_PSRR_MODE;
+
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_SW_HIGH_PSRR_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ REG_LAB_SW_HIGH_PSRR_CTL, rc);
+ return rc;
+ }
+ }
+
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-lab-ldo-pulldown-enable", (u32 *)&val);
+ if (!rc) {
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_LDO_PD_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ REG_LAB_LDO_PD_CTL, rc);
+ return rc;
+ }
+ }
+
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-lab-high-psrr-src-select", &tmp);
+ if (!rc) {
+ val = tmp;
+
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-lab-vref-high-psrr-select", &tmp);
+ if (rc < 0) {
+ pr_err("get qcom,qpnp-lab-vref-high-psrr-select failed rc = %d\n",
+ rc);
+ return rc;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(lab_vref_high_psrr_table); i++)
+ if (lab_vref_high_psrr_table[i] == tmp)
+ break;
+
+ if (i == ARRAY_SIZE(lab_vref_high_psrr_table)) {
+ pr_err("Invalid value in qpnp-lab-vref-high-psrr-selct\n");
+ return -EINVAL;
+ }
+ val |= (i << LAB_SEL_HW_HIGH_PSRR_SRC_SHIFT);
+
+ rc = qpnp_labibb_masked_write(labibb, labibb->lab_base +
+ REG_LAB_VPH_ENVELOP_CTL,
+ LAB_VREF_HIGH_PSRR_SEL_MASK |
+ LAB_SEL_HW_HIGH_PSRR_SRC_MASK,
+ val);
+
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ REG_LAB_VPH_ENVELOP_CTL, rc);
+ return rc;
+ }
+ }
+
+ if (labibb->swire_control) {
+ rc = qpnp_ibb_set_mode(labibb, IBB_HW_CONTROL);
+ if (rc < 0) {
+ pr_err("Unable to set SWIRE_RDY rc=%d\n", rc);
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+#define LAB_CURRENT_MAX_1600MA 0x7
+#define LAB_CURRENT_MAX_400MA 0x1
+static int qpnp_lab_pfm_disable(struct qpnp_labibb *labibb)
+{
+ int rc = 0;
+ u8 val, mask;
+
+ mutex_lock(&(labibb->lab_vreg.lab_mutex));
+ if (!labibb->pfm_enable) {
+ pr_debug("PFM already disabled\n");
+ goto out;
+ }
+
+ val = 0;
+ mask = LAB_PFM_EN_BIT;
+ rc = qpnp_labibb_masked_write(labibb, labibb->lab_base +
+ REG_LAB_PFM_CTL, mask, val);
+ if (rc < 0) {
+ pr_err("Write register %x failed rc = %d\n",
+ REG_LAB_PFM_CTL, rc);
+ goto out;
+ }
+
+ val = LAB_CURRENT_MAX_1600MA;
+ mask = LAB_OVERRIDE_CURRENT_MAX_BIT | LAB_CURRENT_LIMIT_MASK;
+ rc = qpnp_labibb_masked_write(labibb, labibb->lab_base +
+ REG_LAB_CURRENT_LIMIT, mask, val);
+ if (rc < 0) {
+ pr_err("Write register %x failed rc = %d\n",
+ REG_LAB_CURRENT_LIMIT, rc);
+ goto out;
+ }
+
+ labibb->pfm_enable = false;
+out:
+ mutex_unlock(&(labibb->lab_vreg.lab_mutex));
+ return rc;
+}
+
+static int qpnp_lab_pfm_enable(struct qpnp_labibb *labibb)
+{
+ int rc = 0;
+ u8 val, mask;
+
+ mutex_lock(&(labibb->lab_vreg.lab_mutex));
+ if (labibb->pfm_enable) {
+ pr_debug("PFM already enabled\n");
+ goto out;
+ }
+
+ /* Wait for ~100uS */
+ usleep_range(100, 105);
+
+ val = LAB_OVERRIDE_CURRENT_MAX_BIT | LAB_CURRENT_MAX_400MA;
+ mask = LAB_OVERRIDE_CURRENT_MAX_BIT | LAB_CURRENT_LIMIT_MASK;
+ rc = qpnp_labibb_masked_write(labibb, labibb->lab_base +
+ REG_LAB_CURRENT_LIMIT, mask, val);
+ if (rc < 0) {
+ pr_err("Write register %x failed rc = %d\n",
+ REG_LAB_CURRENT_LIMIT, rc);
+ goto out;
+ }
+
+ /* Wait for ~100uS */
+ usleep_range(100, 105);
+
+ val = LAB_PFM_EN_BIT;
+ mask = LAB_PFM_EN_BIT;
+ rc = qpnp_labibb_masked_write(labibb, labibb->lab_base +
+ REG_LAB_PFM_CTL, mask, val);
+ if (rc < 0) {
+ pr_err("Write register %x failed rc = %d\n",
+ REG_LAB_PFM_CTL, rc);
+ goto out;
+ }
+
+ labibb->pfm_enable = true;
+out:
+ mutex_unlock(&(labibb->lab_vreg.lab_mutex));
+ return rc;
+}
+
+static int qpnp_labibb_restore_settings(struct qpnp_labibb *labibb)
+{
+ int rc, i;
+
+ for (i = 0; i < ARRAY_SIZE(ibb_settings); i++) {
+ if (ibb_settings[i].sec_access)
+ rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base,
+ ibb_settings[i].address,
+ ibb_settings[i].value);
+ else
+ rc = qpnp_labibb_write(labibb, labibb->ibb_base +
+ ibb_settings[i].address,
+ &ibb_settings[i].value, 1);
+
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ ibb_settings[i].address, rc);
+ return rc;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(lab_settings); i++) {
+ if (lab_settings[i].sec_access)
+ rc = qpnp_labibb_sec_write(labibb, labibb->lab_base,
+ lab_settings[i].address,
+ lab_settings[i].value);
+ else
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ lab_settings[i].address,
+ &lab_settings[i].value, 1);
+
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ lab_settings[i].address, rc);
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+static int qpnp_labibb_save_settings(struct qpnp_labibb *labibb)
+{
+ int rc, i;
+
+ for (i = 0; i < ARRAY_SIZE(ibb_settings); i++) {
+ rc = qpnp_labibb_read(labibb, labibb->ibb_base +
+ ibb_settings[i].address, &ibb_settings[i].value, 1);
+ if (rc < 0) {
+ pr_err("read register %x failed rc = %d\n",
+ ibb_settings[i].address, rc);
+ return rc;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(lab_settings); i++) {
+ rc = qpnp_labibb_read(labibb, labibb->lab_base +
+ lab_settings[i].address, &lab_settings[i].value, 1);
+ if (rc < 0) {
+ pr_err("read register %x failed rc = %d\n",
+ lab_settings[i].address, rc);
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+static int qpnp_labibb_ttw_enter_ibb_common(struct qpnp_labibb *labibb)
+{
+ int rc = 0;
+ u8 val;
+
+ val = 0;
+ rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_PD_CTL,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("read register %x failed rc = %d\n",
+ REG_IBB_PD_CTL, rc);
+ return rc;
+ }
+
+ val = 0;
+ rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base,
+ REG_IBB_PWRUP_PWRDN_CTL_1, val);
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ REG_IBB_PWRUP_PWRDN_CTL_1, rc);
+ return rc;
+ }
+
+ val = IBB_WAIT_MBG_OK;
+ rc = qpnp_labibb_sec_masked_write(labibb, labibb->ibb_base,
+ REG_IBB_PWRUP_PWRDN_CTL_2,
+ IBB_DIS_DLY_MASK | IBB_WAIT_MBG_OK, val);
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ REG_IBB_PWRUP_PWRDN_CTL_2, rc);
+ return rc;
+ }
+
+ val = IBB_NFET_SLEW_EN | IBB_PFET_SLEW_EN | IBB_OVERRIDE_NFET_SW_SIZE |
+ IBB_OVERRIDE_PFET_SW_SIZE;
+ rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base +
+ REG_IBB_RDSON_MNGMNT, 0xFF, val);
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ REG_IBB_RDSON_MNGMNT, rc);
+ return rc;
+ }
+
+ val = IBB_CURRENT_LIMIT_EN | IBB_CURRENT_MAX_500MA |
+ (IBB_ILIMIT_COUNT_CYC8 << IBB_CURRENT_LIMIT_DEBOUNCE_SHIFT);
+ rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base,
+ REG_IBB_CURRENT_LIMIT, val);
+ if (rc < 0)
+ pr_err("write to register %x failed rc = %d\n",
+ REG_IBB_CURRENT_LIMIT, rc);
+
+ return rc;
+}
+
+static int qpnp_labibb_ttw_enter_ibb_pmi8996(struct qpnp_labibb *labibb)
+{
+ int rc;
+ u8 val;
+
+ val = IBB_BYPASS_PWRDN_DLY2_BIT | IBB_FAST_STARTUP;
+ rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_SPARE_CTL,
+ &val, 1);
+ if (rc < 0)
+ pr_err("write to register %x failed rc = %d\n",
+ REG_IBB_SPARE_CTL, rc);
+
+ return rc;
+}
+
+static int qpnp_labibb_ttw_enter_ibb_pmi8950(struct qpnp_labibb *labibb)
+{
+ int rc;
+ u8 val;
+
+ rc = qpnp_ibb_ps_config(labibb, true);
+ if (rc < 0) {
+ pr_err("Failed to enable ibb_ps_config rc=%d\n", rc);
+ return rc;
+ }
+
+ val = IBB_SOFT_START_CHARGING_RESISTOR_16K;
+ rc = qpnp_labibb_write(labibb, labibb->ibb_base +
+ REG_IBB_SOFT_START_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ REG_IBB_SOFT_START_CTL, rc);
+ return rc;
+ }
+
+ val = IBB_MODULE_RDY_EN;
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_IBB_MODULE_RDY, &val, 1);
+ if (rc < 0)
+ pr_err("write to register %x failed rc = %d\n",
+ REG_IBB_MODULE_RDY, rc);
+
+ return rc;
+}
+
+static int qpnp_labibb_regulator_ttw_mode_enter(struct qpnp_labibb *labibb)
+{
+ int rc = 0;
+ u8 val;
+
+ /* Save the IBB settings before they get modified for TTW mode */
+ if (!labibb->ibb_settings_saved) {
+ rc = qpnp_labibb_save_settings(labibb);
+ if (rc) {
+ pr_err("Error in storing IBB setttings, rc=%d\n", rc);
+ return rc;
+ }
+ labibb->ibb_settings_saved = true;
+ }
+
+ if (labibb->ttw_force_lab_on) {
+ val = LAB_MODULE_RDY_EN;
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_MODULE_RDY, &val, 1);
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ REG_LAB_MODULE_RDY, rc);
+ return rc;
+ }
+
+ /* Prevents LAB being turned off by IBB */
+ val = LAB_ENABLE_CTL_EN;
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_ENABLE_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ REG_LAB_ENABLE_CTL, rc);
+ return rc;
+ }
+
+ val = LAB_RDSON_MNGMNT_NFET_SLEW_EN |
+ LAB_RDSON_MNGMNT_PFET_SLEW_EN |
+ LAB_RDSON_NFET_SW_SIZE_QUARTER |
+ LAB_RDSON_PFET_SW_SIZE_QUARTER;
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_RDSON_MNGMNT, &val, 1);
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ REG_LAB_RDSON_MNGMNT, rc);
+ return rc;
+ }
+
+ rc = qpnp_labibb_masked_write(labibb, labibb->lab_base +
+ REG_LAB_PS_CTL, LAB_PS_CTL_EN, LAB_PS_CTL_EN);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_write register %x failed rc = %d\n",
+ REG_LAB_PS_CTL, rc);
+ return rc;
+ }
+ } else {
+ val = LAB_PD_CTL_DISABLE_PD;
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_PD_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_write register %x failed rc = %d\n",
+ REG_LAB_PD_CTL, rc);
+ return rc;
+ }
+
+ val = LAB_SPARE_DISABLE_SCP_BIT;
+ if (labibb->pmic_rev_id->pmic_subtype != PMI8950_SUBTYPE)
+ val |= LAB_SPARE_TOUCH_WAKE_BIT;
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_SPARE_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_write register %x failed rc = %d\n",
+ REG_LAB_SPARE_CTL, rc);
+ return rc;
+ }
+
+ val = 0;
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_SOFT_START_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_write register %x failed rc = %d\n",
+ REG_LAB_SOFT_START_CTL, rc);
+ return rc;
+ }
+ }
+
+ rc = qpnp_labibb_ttw_enter_ibb_common(labibb);
+ if (rc) {
+ pr_err("Failed to apply TTW ibb common settings rc=%d\n", rc);
+ return rc;
+ }
+
+ switch (labibb->pmic_rev_id->pmic_subtype) {
+ case PMI8996_SUBTYPE:
+ rc = qpnp_labibb_ttw_enter_ibb_pmi8996(labibb);
+ break;
+ case PMI8950_SUBTYPE:
+ rc = qpnp_labibb_ttw_enter_ibb_pmi8950(labibb);
+ break;
+ }
+ if (rc < 0) {
+ pr_err("Failed to configure TTW-enter for IBB rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = qpnp_ibb_set_mode(labibb, IBB_HW_CONTROL);
+ if (rc < 0) {
+ pr_err("Unable to set SWIRE_RDY rc = %d\n", rc);
+ return rc;
+ }
+ labibb->in_ttw_mode = true;
+ return 0;
+}
+
+static int qpnp_labibb_ttw_exit_ibb_common(struct qpnp_labibb *labibb)
+{
+ int rc;
+ u8 val;
+
+ val = IBB_FASTER_PFET_OFF;
+ rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_SPARE_CTL,
+ &val, 1);
+ if (rc < 0)
+ pr_err("qpnp_labibb_write register %x failed rc = %d\n",
+ REG_IBB_SPARE_CTL, rc);
+
+ return rc;
+}
+
+static int qpnp_labibb_regulator_ttw_mode_exit(struct qpnp_labibb *labibb)
+{
+ int rc = 0;
+ u8 val;
+
+ if (!labibb->ibb_settings_saved) {
+ pr_err("IBB settings are not saved!\n");
+ return -EINVAL;
+ }
+
+ /* Restore the IBB settings back to switch back to normal mode */
+ rc = qpnp_labibb_restore_settings(labibb);
+ if (rc < 0) {
+ pr_err("Error in restoring IBB setttings, rc=%d\n", rc);
+ return rc;
+ }
+
+ if (labibb->ttw_force_lab_on) {
+ val = 0;
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_ENABLE_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_write register %x failed rc = %d\n",
+ REG_LAB_ENABLE_CTL, rc);
+ return rc;
+ }
+ } else {
+ val = LAB_PD_CTL_STRONG_PULL;
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_PD_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_write register %x failed rc = %d\n",
+ REG_LAB_PD_CTL, rc);
+ return rc;
+ }
+
+ val = 0;
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_SPARE_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_write register %x failed rc = %d\n",
+ REG_LAB_SPARE_CTL, rc);
+ return rc;
+ }
+ }
+
+ switch (labibb->pmic_rev_id->pmic_subtype) {
+ case PMI8996_SUBTYPE:
+ case PMI8994_SUBTYPE:
+ case PMI8950_SUBTYPE:
+ rc = qpnp_labibb_ttw_exit_ibb_common(labibb);
+ break;
+ }
+ if (rc < 0) {
+ pr_err("Failed to configure TTW-exit for IBB rc=%d\n", rc);
+ return rc;
+ }
+
+ labibb->in_ttw_mode = false;
+ return rc;
+}
+
+static int qpnp_labibb_regulator_enable(struct qpnp_labibb *labibb)
+{
+ int rc;
+ u8 val;
+ int dly;
+ int retries;
+ bool enabled = false;
+
+ if (labibb->ttw_en && !labibb->ibb_vreg.vreg_enabled &&
+ labibb->in_ttw_mode) {
+ rc = qpnp_labibb_regulator_ttw_mode_exit(labibb);
+ if (rc) {
+ pr_err("Error in exiting TTW mode rc = %d\n", rc);
+ return rc;
+ }
+ }
+
+ rc = qpnp_ibb_set_mode(labibb, IBB_SW_CONTROL_EN);
+ if (rc) {
+ pr_err("Unable to set IBB_MODULE_EN rc = %d\n", rc);
+ return rc;
+ }
+
+ /* total delay time */
+ dly = labibb->lab_vreg.soft_start + labibb->ibb_vreg.soft_start
+ + labibb->ibb_vreg.pwrup_dly;
+ usleep_range(dly, dly + 100);
+
+ /* after this delay, lab should be enabled */
+ rc = qpnp_labibb_read(labibb, labibb->lab_base + REG_LAB_STATUS1,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("read register %x failed rc = %d\n",
+ REG_LAB_STATUS1, rc);
+ goto err_out;
+ }
+
+ pr_debug("soft=%d %d up=%d dly=%d\n",
+ labibb->lab_vreg.soft_start, labibb->ibb_vreg.soft_start,
+ labibb->ibb_vreg.pwrup_dly, dly);
+
+ if (!(val & LAB_STATUS1_VREG_OK)) {
+ pr_err("failed for LAB %x\n", val);
+ goto err_out;
+ }
+
+ /* poll IBB_STATUS to make sure ibb had been enabled */
+ dly = labibb->ibb_vreg.soft_start + labibb->ibb_vreg.pwrup_dly;
+ retries = 10;
+ while (retries--) {
+ rc = qpnp_labibb_read(labibb, labibb->ibb_base +
+ REG_IBB_STATUS1, &val, 1);
+ if (rc < 0) {
+ pr_err("read register %x failed rc = %d\n",
+ REG_IBB_STATUS1, rc);
+ goto err_out;
+ }
+
+ if (val & IBB_STATUS1_VREG_OK) {
+ enabled = true;
+ break;
+ }
+ usleep_range(dly, dly + 100);
+ }
+
+ if (!enabled) {
+ pr_err("failed for IBB %x\n", val);
+ goto err_out;
+ }
+
+ labibb->lab_vreg.vreg_enabled = 1;
+ labibb->ibb_vreg.vreg_enabled = 1;
+
+ return 0;
+err_out:
+ rc = qpnp_ibb_set_mode(labibb, IBB_SW_CONTROL_DIS);
+ if (rc < 0) {
+ pr_err("Unable to set IBB_MODULE_EN rc = %d\n", rc);
+ return rc;
+ }
+ return -EINVAL;
+}
+
+static int qpnp_labibb_regulator_disable(struct qpnp_labibb *labibb)
+{
+ int rc;
+ u8 val;
+ int dly;
+ int retries;
+ bool disabled = false;
+
+ /*
+ * When TTW mode is enabled and LABIBB regulators are disabled, it is
+ * recommended not to disable IBB through IBB_ENABLE_CTL when switching
+ * to SWIRE control on entering TTW mode. Hence, just enter TTW mode
+ * and mark the regulators disabled. When we exit TTW mode, normal
+ * mode settings will be restored anyways and regulators will be
+ * enabled as before.
+ */
+ if (labibb->ttw_en && !labibb->in_ttw_mode) {
+ rc = qpnp_labibb_regulator_ttw_mode_enter(labibb);
+ if (rc < 0) {
+ pr_err("Error in entering TTW mode rc = %d\n", rc);
+ return rc;
+ }
+ labibb->lab_vreg.vreg_enabled = 0;
+ labibb->ibb_vreg.vreg_enabled = 0;
+ return 0;
+ }
+
+ rc = qpnp_ibb_set_mode(labibb, IBB_SW_CONTROL_DIS);
+ if (rc < 0) {
+ pr_err("Unable to set IBB_MODULE_EN rc = %d\n", rc);
+ return rc;
+ }
+
+ /* poll IBB_STATUS to make sure ibb had been disabled */
+ dly = labibb->ibb_vreg.pwrdn_dly;
+ retries = 2;
+ while (retries--) {
+ usleep_range(dly, dly + 100);
+ rc = qpnp_labibb_read(labibb, labibb->ibb_base +
+ REG_IBB_STATUS1, &val, 1);
+ if (rc < 0) {
+ pr_err("read register %x failed rc = %d\n",
+ REG_IBB_STATUS1, rc);
+ return rc;
+ }
+
+ if (!(val & IBB_STATUS1_VREG_OK)) {
+ disabled = true;
+ break;
+ }
+ }
+
+ if (!disabled) {
+ pr_err("failed for IBB %x\n", val);
+ return -EINVAL;
+ }
+
+ if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE &&
+ labibb->mode == QPNP_LABIBB_LCD_MODE) {
+ rc = qpnp_lab_pfm_disable(labibb);
+ if (rc < 0) {
+ pr_err("Error in disabling PFM, rc=%d\n", rc);
+ return rc;
+ }
+ }
+
+ labibb->lab_vreg.vreg_enabled = 0;
+ labibb->ibb_vreg.vreg_enabled = 0;
+
+ return 0;
+}
+
+static int qpnp_lab_regulator_enable(struct regulator_dev *rdev)
+{
+ int rc;
+ u8 val;
+
+ struct qpnp_labibb *labibb = rdev_get_drvdata(rdev);
+
+ if (labibb->skip_2nd_swire_cmd) {
+ rc = qpnp_ibb_ps_config(labibb, false);
+ if (rc < 0) {
+ pr_err("Failed to disable IBB PS rc=%d\n", rc);
+ return rc;
+ }
+ }
+
+ if (!labibb->lab_vreg.vreg_enabled && !labibb->swire_control) {
+
+ if (!labibb->standalone)
+ return qpnp_labibb_regulator_enable(labibb);
+
+ val = LAB_ENABLE_CTL_EN;
+ rc = qpnp_labibb_write(labibb,
+ labibb->lab_base + REG_LAB_ENABLE_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_lab_regulator_enable write register %x failed rc = %d\n",
+ REG_LAB_ENABLE_CTL, rc);
+ return rc;
+ }
+
+ udelay(labibb->lab_vreg.soft_start);
+
+ rc = qpnp_labibb_read(labibb, labibb->lab_base +
+ REG_LAB_STATUS1, &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_lab_regulator_enable read register %x failed rc = %d\n",
+ REG_LAB_STATUS1, rc);
+ return rc;
+ }
+
+ if ((val & LAB_STATUS1_VREG_OK_MASK) != LAB_STATUS1_VREG_OK) {
+ pr_err("qpnp_lab_regulator_enable failed\n");
+ return -EINVAL;
+ }
+
+ labibb->lab_vreg.vreg_enabled = 1;
+ }
+
+ return 0;
+}
+
+static int qpnp_lab_regulator_disable(struct regulator_dev *rdev)
+{
+ int rc;
+ u8 val;
+ struct qpnp_labibb *labibb = rdev_get_drvdata(rdev);
+
+ if (labibb->lab_vreg.vreg_enabled && !labibb->swire_control) {
+
+ if (!labibb->standalone)
+ return qpnp_labibb_regulator_disable(labibb);
+
+ val = 0;
+ rc = qpnp_labibb_write(labibb,
+ labibb->lab_base + REG_LAB_ENABLE_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_lab_regulator_enable write register %x failed rc = %d\n",
+ REG_LAB_ENABLE_CTL, rc);
+ return rc;
+ }
+
+ labibb->lab_vreg.vreg_enabled = 0;
+ }
+ return 0;
+}
+
+static int qpnp_lab_regulator_is_enabled(struct regulator_dev *rdev)
+{
+ struct qpnp_labibb *labibb = rdev_get_drvdata(rdev);
+
+ if (labibb->swire_control)
+ return 0;
+
+ return labibb->lab_vreg.vreg_enabled;
+}
+
+static int qpnp_lab_regulator_set_voltage(struct regulator_dev *rdev,
+ int min_uV, int max_uV, unsigned int *selector)
+{
+ int rc, new_uV;
+ u8 val;
+ struct qpnp_labibb *labibb = rdev_get_drvdata(rdev);
+
+ if (labibb->swire_control)
+ return 0;
+
+ if (min_uV < labibb->lab_vreg.min_volt) {
+ pr_err("min_uV %d is less than min_volt %d", min_uV,
+ labibb->lab_vreg.min_volt);
+ return -EINVAL;
+ }
+
+ val = DIV_ROUND_UP(min_uV - labibb->lab_vreg.min_volt,
+ labibb->lab_vreg.step_size);
+ new_uV = val * labibb->lab_vreg.step_size + labibb->lab_vreg.min_volt;
+
+ if (new_uV > max_uV) {
+ pr_err("unable to set voltage %d (min:%d max:%d)\n", new_uV,
+ min_uV, max_uV);
+ return -EINVAL;
+ }
+
+ rc = qpnp_labibb_masked_write(labibb, labibb->lab_base +
+ REG_LAB_VOLTAGE,
+ LAB_VOLTAGE_SET_MASK |
+ LAB_VOLTAGE_OVERRIDE_EN,
+ val | LAB_VOLTAGE_OVERRIDE_EN);
+
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n", REG_LAB_VOLTAGE,
+ rc);
+ return rc;
+ }
+
+ if (new_uV > labibb->lab_vreg.curr_volt) {
+ val = DIV_ROUND_UP(new_uV - labibb->lab_vreg.curr_volt,
+ labibb->lab_vreg.step_size);
+ udelay(val * labibb->lab_vreg.slew_rate);
+ }
+ labibb->lab_vreg.curr_volt = new_uV;
+
+ return 0;
+}
+
+static int qpnp_skip_swire_command(struct qpnp_labibb *labibb)
+{
+ int rc = 0, retry = 50, dly;
+ u8 reg;
+
+ do {
+ /* poll for ibb vreg_ok */
+ rc = qpnp_labibb_read(labibb, labibb->ibb_base +
+ REG_IBB_STATUS1, ®, 1);
+ if (rc < 0) {
+ pr_err("Failed to read ibb_status1 reg rc=%d\n", rc);
+ return rc;
+ }
+ if ((reg & IBB_STATUS1_VREG_OK_MASK) == IBB_STATUS1_VREG_OK)
+ break;
+
+ /* poll delay */
+ usleep_range(500, 600);
+
+ } while (--retry);
+
+ if (!retry) {
+ pr_err("ibb vreg_ok failed to turn-on\n");
+ return -EBUSY;
+ }
+
+ /* move to SW control */
+ rc = qpnp_ibb_set_mode(labibb, IBB_SW_CONTROL_EN);
+ if (rc < 0) {
+ pr_err("Failed switch to IBB_SW_CONTROL rc=%d\n", rc);
+ return rc;
+ }
+
+ /* delay to skip the second swire command */
+ dly = labibb->swire_2nd_cmd_delay * 1000;
+ while (dly / 20000) {
+ usleep_range(20000, 20010);
+ dly -= 20000;
+ }
+ if (dly)
+ usleep_range(dly, dly + 10);
+
+ rc = qpnp_ibb_set_mode(labibb, IBB_HW_SW_CONTROL);
+ if (rc < 0) {
+ pr_err("Failed switch to IBB_HW_SW_CONTROL rc=%d\n", rc);
+ return rc;
+ }
+
+ /* delay for SPMI to SWIRE transition */
+ usleep_range(1000, 1100);
+
+ /* Move back to SWIRE control */
+ rc = qpnp_ibb_set_mode(labibb, IBB_HW_CONTROL);
+ if (rc < 0)
+ pr_err("Failed switch to IBB_HW_CONTROL rc=%d\n", rc);
+
+ /* delay before enabling the PS mode */
+ msleep(labibb->swire_ibb_ps_enable_delay);
+ rc = qpnp_ibb_ps_config(labibb, true);
+ if (rc < 0)
+ pr_err("Unable to enable IBB PS rc=%d\n", rc);
+
+ return rc;
+}
+
+static irqreturn_t lab_vreg_ok_handler(int irq, void *_labibb)
+{
+ struct qpnp_labibb *labibb = _labibb;
+ int rc;
+
+ if (labibb->skip_2nd_swire_cmd && labibb->lab_dig_major < 2) {
+ rc = qpnp_skip_swire_command(labibb);
+ if (rc < 0)
+ pr_err("Failed in 'qpnp_skip_swire_command' rc=%d\n",
+ rc);
+ } else if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE &&
+ labibb->mode == QPNP_LABIBB_LCD_MODE) {
+ rc = qpnp_lab_pfm_enable(labibb);
+ if (rc < 0)
+ pr_err("Failed to config PFM, rc=%d\n", rc);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int qpnp_lab_regulator_get_voltage(struct regulator_dev *rdev)
+{
+ struct qpnp_labibb *labibb = rdev_get_drvdata(rdev);
+
+ if (labibb->swire_control)
+ return 0;
+
+ return labibb->lab_vreg.curr_volt;
+}
+
+static bool is_lab_vreg_ok_irq_available(struct qpnp_labibb *labibb)
+{
+ /*
+ * LAB VREG_OK interrupt is used only to skip 2nd SWIRE command in
+ * dig_major < 2 targets. For pmi8998, it is used to enable PFM in
+ * LCD mode.
+ */
+ if (labibb->skip_2nd_swire_cmd && labibb->lab_dig_major < 2)
+ return true;
+
+ if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE &&
+ labibb->mode == QPNP_LABIBB_LCD_MODE)
+ return true;
+
+ return false;
+}
+
+static struct regulator_ops qpnp_lab_ops = {
+ .enable = qpnp_lab_regulator_enable,
+ .disable = qpnp_lab_regulator_disable,
+ .is_enabled = qpnp_lab_regulator_is_enabled,
+ .set_voltage = qpnp_lab_regulator_set_voltage,
+ .get_voltage = qpnp_lab_regulator_get_voltage,
+};
+
+static int register_qpnp_lab_regulator(struct qpnp_labibb *labibb,
+ struct device_node *of_node)
+{
+ int rc = 0;
+ struct regulator_init_data *init_data;
+ struct regulator_desc *rdesc = &labibb->lab_vreg.rdesc;
+ struct regulator_config cfg = {};
+ u8 val, mask;
+ const char *current_sense_str;
+ bool config_current_sense = false;
+ u32 tmp;
+
+ if (!of_node) {
+ dev_err(labibb->dev, "qpnp lab regulator device tree node is missing\n");
+ return -EINVAL;
+ }
+
+ init_data = of_get_regulator_init_data(labibb->dev, of_node, rdesc);
+ if (!init_data) {
+ pr_err("unable to get regulator init data for qpnp lab regulator\n");
+ return -ENOMEM;
+ }
+
+ rc = of_property_read_u32(of_node, "qcom,qpnp-lab-min-voltage",
+ &(labibb->lab_vreg.min_volt));
+ if (rc < 0) {
+ pr_err("qcom,qpnp-lab-min-voltage is missing, rc = %d\n",
+ rc);
+ return rc;
+ }
+
+ rc = of_property_read_u32(of_node, "qcom,qpnp-lab-step-size",
+ &(labibb->lab_vreg.step_size));
+ if (rc < 0) {
+ pr_err("qcom,qpnp-lab-step-size is missing, rc = %d\n", rc);
+ return rc;
+ }
+
+ rc = of_property_read_u32(of_node, "qcom,qpnp-lab-slew-rate",
+ &(labibb->lab_vreg.slew_rate));
+ if (rc < 0) {
+ pr_err("qcom,qpnp-lab-slew-rate is missing, rc = %d\n",
+ rc);
+ return rc;
+ }
+
+ rc = of_property_read_u32(of_node, "qcom,qpnp-lab-soft-start",
+ &(labibb->lab_vreg.soft_start));
+ if (!rc) {
+ for (val = 0; val < ARRAY_SIZE(lab_soft_start_table); val++)
+ if (lab_soft_start_table[val] ==
+ labibb->lab_vreg.soft_start)
+ break;
+
+ if (val == ARRAY_SIZE(lab_soft_start_table))
+ val = ARRAY_SIZE(lab_soft_start_table) - 1;
+
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_SOFT_START_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_write register %x failed rc = %d\n",
+ REG_LAB_SOFT_START_CTL, rc);
+ return rc;
+ }
+
+ labibb->lab_vreg.soft_start = lab_soft_start_table
+ [val & LAB_SOFT_START_CTL_MASK];
+ }
+
+ val = 0;
+ mask = 0;
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-lab-max-precharge-time", &tmp);
+ if (!rc) {
+ for (val = 0; val < ARRAY_SIZE(lab_max_precharge_table); val++)
+ if (lab_max_precharge_table[val] == tmp)
+ break;
+
+ if (val == ARRAY_SIZE(lab_max_precharge_table)) {
+ pr_err("Invalid value in qcom,qpnp-lab-max-precharge-time\n");
+ return -EINVAL;
+ }
+
+ mask = LAB_MAX_PRECHARGE_TIME_MASK;
+ }
+
+ if (of_property_read_bool(of_node,
+ "qcom,qpnp-lab-max-precharge-enable")) {
+ val |= LAB_FAST_PRECHARGE_CTL_EN;
+ mask |= LAB_FAST_PRECHARGE_CTL_EN;
+ }
+
+ rc = qpnp_labibb_masked_write(labibb, labibb->lab_base +
+ REG_LAB_PRECHARGE_CTL, mask, val);
+ if (rc < 0) {
+ pr_err("qpnp_lab_dt_init write register %x failed rc = %d\n",
+ REG_LAB_PRECHARGE_CTL, rc);
+ return rc;
+ }
+
+ if (labibb->mode == QPNP_LABIBB_AMOLED_MODE &&
+ labibb->pmic_rev_id->pmic_subtype != PM660L_SUBTYPE) {
+ /*
+ * default to 1.5 times current gain if
+ * user doesn't specify the current-sense
+ * dt parameter
+ */
+ current_sense_str = "1.5x";
+ val = qpnp_labibb_get_matching_idx(current_sense_str);
+ config_current_sense = true;
+ }
+
+ if (of_find_property(of_node,
+ "qcom,qpnp-lab-current-sense", NULL)) {
+ config_current_sense = true;
+ rc = of_property_read_string(of_node,
+ "qcom,qpnp-lab-current-sense",
+ ¤t_sense_str);
+ if (!rc) {
+ val = qpnp_labibb_get_matching_idx(
+ current_sense_str);
+ } else {
+ pr_err("qcom,qpnp-lab-current-sense configured incorrectly rc = %d\n",
+ rc);
+ return rc;
+ }
+ }
+
+ if (config_current_sense) {
+ rc = qpnp_labibb_masked_write(labibb, labibb->lab_base +
+ REG_LAB_CURRENT_SENSE,
+ LAB_CURRENT_SENSE_GAIN_MASK,
+ val);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_write register %x failed rc = %d\n",
+ REG_LAB_CURRENT_SENSE, rc);
+ return rc;
+ }
+ }
+
+ val = (labibb->standalone) ? 0 : LAB_IBB_EN_RDY_EN;
+ rc = qpnp_labibb_sec_write(labibb, labibb->lab_base,
+ REG_LAB_IBB_EN_RDY, val);
+
+ if (rc < 0) {
+ pr_err("qpnp_lab_sec_write register %x failed rc = %d\n",
+ REG_LAB_IBB_EN_RDY, rc);
+ return rc;
+ }
+
+ rc = qpnp_labibb_read(labibb, labibb->ibb_base + REG_IBB_ENABLE_CTL,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_read register %x failed rc = %d\n",
+ REG_IBB_ENABLE_CTL, rc);
+ return rc;
+ }
+
+ if (!(val & (IBB_ENABLE_CTL_SWIRE_RDY | IBB_ENABLE_CTL_MODULE_EN))) {
+ /* SWIRE_RDY and IBB_MODULE_EN not enabled */
+ rc = qpnp_lab_dt_init(labibb, of_node);
+ if (rc < 0) {
+ pr_err("qpnp-lab: wrong DT parameter specified: rc = %d\n",
+ rc);
+ return rc;
+ }
+ } else {
+ rc = labibb->ibb_ver_ops->get_mode(labibb);
+
+ rc = qpnp_labibb_read(labibb, labibb->lab_base +
+ REG_LAB_VOLTAGE, &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_lab_read read register %x failed rc = %d\n",
+ REG_LAB_VOLTAGE, rc);
+ return rc;
+ }
+
+ labibb->lab_vreg.curr_volt =
+ (val &
+ LAB_VOLTAGE_SET_MASK) *
+ labibb->lab_vreg.step_size +
+ labibb->lab_vreg.min_volt;
+ if (labibb->mode == QPNP_LABIBB_LCD_MODE) {
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-lab-init-lcd-voltage",
+ &(labibb->lab_vreg.curr_volt));
+ if (rc < 0) {
+ pr_err("get qcom,qpnp-lab-init-lcd-voltage failed, rc = %d\n",
+ rc);
+ return rc;
+ }
+ } else if (!(val & LAB_VOLTAGE_OVERRIDE_EN)) {
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-lab-init-amoled-voltage",
+ &(labibb->lab_vreg.curr_volt));
+ if (rc < 0) {
+ pr_err("get qcom,qpnp-lab-init-amoled-voltage failed, rc = %d\n",
+ rc);
+ return rc;
+ }
+ }
+
+ labibb->lab_vreg.vreg_enabled = 1;
+ }
+
+ if (is_lab_vreg_ok_irq_available(labibb)) {
+ rc = devm_request_threaded_irq(labibb->dev,
+ labibb->lab_vreg.lab_vreg_ok_irq, NULL,
+ lab_vreg_ok_handler,
+ IRQF_ONESHOT | IRQF_TRIGGER_RISING,
+ "lab-vreg-ok", labibb);
+ if (rc) {
+ pr_err("Failed to register 'lab-vreg-ok' irq rc=%d\n",
+ rc);
+ return rc;
+ }
+ }
+
+ rc = qpnp_labibb_read(labibb, labibb->lab_base + REG_LAB_MODULE_RDY,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_lab_read read register %x failed rc = %d\n",
+ REG_LAB_MODULE_RDY, rc);
+ return rc;
+ }
+
+ if (!(val & LAB_MODULE_RDY_EN)) {
+ val = LAB_MODULE_RDY_EN;
+
+ rc = qpnp_labibb_write(labibb, labibb->lab_base +
+ REG_LAB_MODULE_RDY, &val, 1);
+
+ if (rc < 0) {
+ pr_err("qpnp_lab_dt_init write register %x failed rc = %d\n",
+ REG_LAB_MODULE_RDY, rc);
+ return rc;
+ }
+ }
+
+ if (init_data->constraints.name) {
+ rdesc->owner = THIS_MODULE;
+ rdesc->type = REGULATOR_VOLTAGE;
+ rdesc->ops = &qpnp_lab_ops;
+ rdesc->name = init_data->constraints.name;
+
+ cfg.dev = labibb->dev;
+ cfg.init_data = init_data;
+ cfg.driver_data = labibb;
+ cfg.of_node = of_node;
+
+ if (of_get_property(labibb->dev->of_node, "parent-supply",
+ NULL))
+ init_data->supply_regulator = "parent";
+
+ init_data->constraints.valid_ops_mask
+ |= REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS;
+
+ labibb->lab_vreg.rdev = regulator_register(rdesc, &cfg);
+ if (IS_ERR(labibb->lab_vreg.rdev)) {
+ rc = PTR_ERR(labibb->lab_vreg.rdev);
+ labibb->lab_vreg.rdev = NULL;
+ pr_err("unable to get regulator init data for qpnp lab regulator, rc = %d\n",
+ rc);
+
+ return rc;
+ }
+ } else {
+ dev_err(labibb->dev, "qpnp lab regulator name missing\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int qpnp_ibb_pfm_mode_enable(struct qpnp_labibb *labibb,
+ struct device_node *of_node)
+{
+ int rc = 0;
+ u32 i, tmp = 0;
+ u8 val = IBB_PFM_ENABLE;
+
+ rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-pfm-peak-curr",
+ &tmp);
+ if (rc < 0) {
+ pr_err("qcom,qpnp-ibb-pfm-peak-curr is missing, rc = %d\n",
+ rc);
+ return rc;
+ }
+ for (i = 0; i < ARRAY_SIZE(ibb_pfm_peak_curr_table); i++)
+ if (ibb_pfm_peak_curr_table[i] == tmp)
+ break;
+
+ if (i == ARRAY_SIZE(ibb_pfm_peak_curr_table)) {
+ pr_err("Invalid value in qcom,qpnp-ibb-pfm-peak-curr\n");
+ return -EINVAL;
+ }
+
+ val |= (i << IBB_PFM_PEAK_CURRENT_BIT_SHIFT);
+
+ rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-pfm-hysteresis",
+ &tmp);
+ if (rc < 0) {
+ pr_err("qcom,qpnp-ibb-pfm-hysteresis is missing, rc = %d\n",
+ rc);
+ return rc;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(ibb_pfm_hysteresis_table); i++)
+ if (ibb_pfm_hysteresis_table[i] == tmp)
+ break;
+
+ if (i == ARRAY_SIZE(ibb_pfm_hysteresis_table)) {
+ pr_err("Invalid value in qcom,qpnp-ibb-pfm-hysteresis\n");
+ return -EINVAL;
+ }
+
+ val |= (i << IBB_PFM_HYSTERESIS_BIT_SHIFT);
+
+ rc = qpnp_labibb_write(labibb, labibb->ibb_base +
+ REG_IBB_PFM_CTL, &val, 1);
+ if (rc < 0)
+ pr_err("qpnp_ibb_pfm_ctl write register %x failed rc = %d\n",
+ REG_IBB_PFM_CTL, rc);
+
+ return rc;
+}
+
+static int qpnp_labibb_pbs_mode_enable(struct qpnp_labibb *labibb,
+ struct device_node *of_node)
+{
+ int rc = 0;
+
+ rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base +
+ REG_IBB_SWIRE_CTL,
+ IBB_SWIRE_VOUT_UPD_EN, 0);
+ if (rc < 0) {
+ pr_err("qpnp_ibb_swire_ctl write register %x failed rc = %d\n",
+ REG_IBB_SWIRE_CTL, rc);
+ return rc;
+ }
+
+ rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base +
+ REG_IBB_PD_CTL, IBB_SWIRE_PD_UPD, 0);
+ if (rc < 0) {
+ pr_err("qpnp_ibb_pd_ctl write register %x failed rc = %d\n",
+ REG_IBB_PD_CTL, rc);
+ return rc;
+ }
+
+ rc = qpnp_labibb_masked_write(labibb, labibb->lab_base +
+ REG_LAB_SWIRE_PGM_CTL, LAB_EN_SWIRE_PGM_VOUT |
+ LAB_EN_SWIRE_PGM_PD, 0);
+ if (rc < 0)
+ pr_err("qpnp_lab_swire_pgm_ctl write register %x failed rc = %d\n",
+ REG_LAB_SWIRE_PGM_CTL, rc);
+
+ return rc;
+}
+
+static int qpnp_ibb_slew_rate_config(struct qpnp_labibb *labibb,
+ struct device_node *of_node)
+{
+ int rc = 0;
+ u32 i, tmp = 0;
+ u8 val = 0, mask = 0;
+
+ rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-fast-slew-rate",
+ &tmp);
+ if (!rc) {
+ for (i = 0; i < ARRAY_SIZE(ibb_output_slew_ctl_table); i++)
+ if (ibb_output_slew_ctl_table[i] == tmp)
+ break;
+
+ if (i == ARRAY_SIZE(ibb_output_slew_ctl_table)) {
+ pr_err("Invalid value in qcom,qpnp-ibb-fast-slew-rate\n");
+ return -EINVAL;
+ }
+
+ labibb->ibb_vreg.slew_rate = tmp;
+ val |= (i << IBB_SLEW_RATE_TRANS_TIME_FAST_SHIFT) |
+ IBB_SLEW_RATE_SPEED_FAST_EN | IBB_SLEW_CTL_EN;
+
+ mask = IBB_SLEW_RATE_SPEED_FAST_EN |
+ IBB_SLEW_RATE_TRANS_TIME_FAST_MASK | IBB_SLEW_CTL_EN;
+ }
+
+ rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-slow-slew-rate",
+ &tmp);
+ if (!rc) {
+ for (i = 0; i < ARRAY_SIZE(ibb_output_slew_ctl_table); i++)
+ if (ibb_output_slew_ctl_table[i] == tmp)
+ break;
+
+ if (i == ARRAY_SIZE(ibb_output_slew_ctl_table)) {
+ pr_err("Invalid value in qcom,qpnp-ibb-slow-slew-rate\n");
+ return -EINVAL;
+ }
+
+ labibb->ibb_vreg.slew_rate = tmp;
+ val |= (i | IBB_SLEW_CTL_EN);
+
+ mask |= IBB_SLEW_RATE_SPEED_FAST_EN |
+ IBB_SLEW_RATE_TRANS_TIME_SLOW_MASK | IBB_SLEW_CTL_EN;
+ }
+
+ rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base +
+ REG_IBB_OUTPUT_SLEW_CTL,
+ mask, val);
+ if (rc < 0)
+ pr_err("qpnp_labibb_write register %x failed rc = %d\n",
+ REG_IBB_OUTPUT_SLEW_CTL, rc);
+
+ return rc;
+}
+
+static bool qpnp_ibb_poff_ctl_required(struct qpnp_labibb *labibb)
+{
+ if (labibb->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE)
+ return false;
+
+ return true;
+}
+
+static int qpnp_ibb_dt_init(struct qpnp_labibb *labibb,
+ struct device_node *of_node)
+{
+ int rc = 0;
+ u32 i, tmp = 0;
+ u8 val, mask;
+
+ /*
+ * Do not configure LCD_AMOLED_SEL for pmi8998 as it will be done by
+ * GPIO selector. Override the labibb->mode with what was configured
+ * by the bootloader.
+ */
+ if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE) {
+ rc = qpnp_labibb_read(labibb, labibb->ibb_base +
+ REG_IBB_LCD_AMOLED_SEL, &val, 1);
+ if (rc) {
+ pr_err("qpnp_labibb_read register %x failed rc = %d\n",
+ REG_IBB_LCD_AMOLED_SEL, rc);
+ return rc;
+ }
+ if (val == REG_LAB_IBB_AMOLED_MODE)
+ labibb->mode = QPNP_LABIBB_AMOLED_MODE;
+ else
+ labibb->mode = QPNP_LABIBB_LCD_MODE;
+ } else {
+ rc = labibb->ibb_ver_ops->sel_mode(labibb, 1);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_sec_write register %x failed rc = %d\n",
+ REG_IBB_LCD_AMOLED_SEL, rc);
+ return rc;
+ }
+ }
+
+ val = 0;
+ mask = 0;
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-ibb-lab-pwrdn-delay", &tmp);
+ if (!rc) {
+ for (val = 0; val < ARRAY_SIZE(ibb_pwrdn_dly_table); val++)
+ if (ibb_pwrdn_dly_table[val] == tmp)
+ break;
+
+ if (val == ARRAY_SIZE(ibb_pwrdn_dly_table)) {
+ pr_err("Invalid value in qcom,qpnp-ibb-lab-pwrdn-delay\n");
+ return -EINVAL;
+ }
+
+ labibb->ibb_vreg.pwrdn_dly = tmp;
+ val |= IBB_PWRUP_PWRDN_CTL_1_EN_DLY2;
+ mask |= IBB_PWRUP_PWRDN_CTL_1_EN_DLY2;
+ }
+
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-ibb-lab-pwrup-delay", &tmp);
+ if (!rc) {
+ for (i = 0; i < ARRAY_SIZE(ibb_pwrup_dly_table); i++)
+ if (ibb_pwrup_dly_table[i] == tmp)
+ break;
+
+ if (i == ARRAY_SIZE(ibb_pwrup_dly_table)) {
+ pr_err("Invalid value in qcom,qpnp-ibb-lab-pwrup-delay\n");
+ return -EINVAL;
+ }
+
+ labibb->ibb_vreg.pwrup_dly = tmp;
+
+ val |= (i << IBB_PWRUP_PWRDN_CTL_1_DLY1_SHIFT);
+ val |= (IBB_PWRUP_PWRDN_CTL_1_EN_DLY1 |
+ IBB_PWRUP_PWRDN_CTL_1_LAB_VREG_OK);
+ mask |= (IBB_PWRUP_PWRDN_CTL_1_EN_DLY1 |
+ IBB_PWRUP_PWRDN_CTL_1_DLY1_MASK |
+ IBB_PWRUP_PWRDN_CTL_1_LAB_VREG_OK);
+ }
+
+ if (of_property_read_bool(of_node,
+ "qcom,qpnp-ibb-en-discharge")) {
+ val |= PWRUP_PWRDN_CTL_1_DISCHARGE_EN;
+ mask |= PWRUP_PWRDN_CTL_1_DISCHARGE_EN;
+ }
+
+ rc = qpnp_labibb_sec_masked_write(labibb, labibb->ibb_base,
+ REG_IBB_PWRUP_PWRDN_CTL_1, mask, val);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_sec_write register %x failed rc = %d\n",
+ REG_IBB_PWRUP_PWRDN_CTL_1, rc);
+ return rc;
+ }
+
+ if (of_property_read_bool(of_node, "qcom,qpnp-ibb-slew-rate-config")) {
+
+ rc = qpnp_ibb_slew_rate_config(labibb, of_node);
+ if (rc < 0)
+ return rc;
+ }
+
+ val = 0;
+ if (!of_property_read_bool(of_node, "qcom,qpnp-ibb-full-pull-down"))
+ val = IBB_PD_CTL_HALF_STRENGTH;
+
+ if (of_property_read_bool(of_node, "qcom,qpnp-ibb-pull-down-enable"))
+ val |= IBB_PD_CTL_EN;
+
+ mask = IBB_PD_CTL_STRENGTH_MASK | IBB_PD_CTL_EN;
+ rc = qpnp_labibb_masked_write(labibb,
+ labibb->ibb_base + REG_IBB_PD_CTL, mask, val);
+
+ if (rc < 0) {
+ pr_err("qpnp_lab_dt_init write register %x failed rc = %d\n",
+ REG_IBB_PD_CTL, rc);
+ return rc;
+ }
+
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-ibb-switching-clock-frequency", &tmp);
+ if (!rc) {
+ for (val = 0; val < ARRAY_SIZE(ibb_clk_div_table); val++)
+ if (ibb_clk_div_table[val] == tmp)
+ break;
+
+ if (val == ARRAY_SIZE(ibb_clk_div_table)) {
+ pr_err("Invalid value in qpnp-ibb-switching-clock-frequency\n");
+ return -EINVAL;
+ }
+ rc = labibb->ibb_ver_ops->set_clk_div(labibb, val);
+ if (rc < 0) {
+ pr_err("qpnp_ibb_dt_init write register %x failed rc = %d\n",
+ REG_IBB_CLK_DIV, rc);
+ return rc;
+ }
+ }
+
+ val = 0;
+ mask = 0;
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-ibb-limit-maximum-current", &tmp);
+ if (!rc) {
+ for (val = 0; val < ARRAY_SIZE(ibb_current_limit_table); val++)
+ if (ibb_current_limit_table[val] == tmp)
+ break;
+
+ if (val == ARRAY_SIZE(ibb_current_limit_table)) {
+ pr_err("Invalid value in qcom,qpnp-ibb-limit-maximum-current\n");
+ return -EINVAL;
+ }
+
+ mask = IBB_CURRENT_LIMIT_MASK;
+ }
+
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-ibb-debounce-cycle", &tmp);
+ if (!rc) {
+ for (i = 0; i < ARRAY_SIZE(ibb_debounce_table); i++)
+ if (ibb_debounce_table[i] == tmp)
+ break;
+
+ if (i == ARRAY_SIZE(ibb_debounce_table)) {
+ pr_err("Invalid value in qcom,qpnp-ibb-debounce-cycle\n");
+ return -EINVAL;
+ }
+
+ val |= (i << IBB_CURRENT_LIMIT_DEBOUNCE_SHIFT);
+ mask |= IBB_CURRENT_LIMIT_DEBOUNCE_MASK;
+ }
+
+ if (of_property_read_bool(of_node,
+ "qcom,qpnp-ibb-limit-max-current-enable")) {
+ val |= IBB_CURRENT_LIMIT_EN;
+ mask |= IBB_CURRENT_LIMIT_EN;
+ }
+
+ rc = qpnp_labibb_sec_masked_write(labibb, labibb->ibb_base,
+ REG_IBB_CURRENT_LIMIT, mask, val);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_sec_write register %x failed rc = %d\n",
+ REG_IBB_CURRENT_LIMIT, rc);
+ return rc;
+ }
+
+ if (of_property_read_bool(of_node,
+ "qcom,qpnp-ibb-ring-suppression-enable")) {
+ val = IBB_RING_SUPPRESSION_CTL_EN;
+ rc = qpnp_labibb_write(labibb, labibb->ibb_base +
+ REG_IBB_RING_SUPPRESSION_CTL,
+ &val,
+ 1);
+ if (rc < 0) {
+ pr_err("qpnp_ibb_dt_init write register %x failed rc = %d\n",
+ REG_IBB_RING_SUPPRESSION_CTL, rc);
+ return rc;
+ }
+ }
+
+ if (of_property_read_bool(of_node, "qcom,qpnp-ibb-ps-enable")) {
+ rc = qpnp_ibb_ps_config(labibb, true);
+ if (rc < 0) {
+ pr_err("qpnp_ibb_dt_init PS enable failed rc=%d\n", rc);
+ return rc;
+ }
+ } else {
+ rc = qpnp_ibb_ps_config(labibb, false);
+ if (rc < 0) {
+ pr_err("qpnp_ibb_dt_init PS disable failed rc=%d\n",
+ rc);
+ return rc;
+ }
+ }
+
+ if (of_property_read_bool(of_node,
+ "qcom,qpnp-ibb-smart-ps-enable")){
+ of_property_read_u32(of_node, "qcom,qpnp-ibb-num-swire-trans",
+ &labibb->ibb_vreg.num_swire_trans);
+
+ of_property_read_u32(of_node,
+ "qcom,qpnp-ibb-neg-curr-limit", &tmp);
+
+ rc = labibb->ibb_ver_ops->smart_ps_config(labibb, true,
+ labibb->ibb_vreg.num_swire_trans, tmp);
+ if (rc < 0) {
+ pr_err("qpnp_ibb_dt_init smart PS enable failed rc=%d\n",
+ rc);
+ return rc;
+ }
+
+ }
+
+ rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-init-voltage",
+ &(labibb->ibb_vreg.curr_volt));
+ if (rc < 0) {
+ pr_err("get qcom,qpnp-ibb-init-voltage failed, rc = %d\n", rc);
+ return rc;
+ }
+
+ if (of_property_read_bool(of_node,
+ "qcom,qpnp-ibb-use-default-voltage"))
+ rc = labibb->ibb_ver_ops->set_default_voltage(labibb, true);
+ else
+ rc = labibb->ibb_ver_ops->set_default_voltage(labibb, false);
+
+ if (rc < 0)
+ return rc;
+
+ if (of_property_read_bool(of_node, "qcom,qpnp-ibb-overload-blank")) {
+ rc = qpnp_ibb_vreg_ok_ctl(labibb, of_node);
+ if (rc < 0)
+ return rc;
+ }
+
+ return 0;
+}
+
+static int qpnp_ibb_regulator_enable(struct regulator_dev *rdev)
+{
+ int rc, delay, retries = 10;
+ u8 val;
+ struct qpnp_labibb *labibb = rdev_get_drvdata(rdev);
+
+ if (!labibb->ibb_vreg.vreg_enabled && !labibb->swire_control) {
+
+ if (!labibb->standalone)
+ return qpnp_labibb_regulator_enable(labibb);
+
+ rc = qpnp_ibb_set_mode(labibb, IBB_SW_CONTROL_EN);
+ if (rc < 0) {
+ pr_err("Unable to set IBB_MODULE_EN rc = %d\n", rc);
+ return rc;
+ }
+
+ delay = labibb->ibb_vreg.soft_start;
+ while (retries--) {
+ /* Wait for a small period before reading IBB_STATUS1 */
+ usleep_range(delay, delay + 100);
+
+ rc = qpnp_labibb_read(labibb, labibb->ibb_base +
+ REG_IBB_STATUS1, &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_ibb_regulator_enable read register %x failed rc = %d\n",
+ REG_IBB_STATUS1, rc);
+ return rc;
+ }
+
+ if (val & IBB_STATUS1_VREG_OK)
+ break;
+ }
+
+ if (!(val & IBB_STATUS1_VREG_OK)) {
+ pr_err("qpnp_ibb_regulator_enable failed\n");
+ return -EINVAL;
+ }
+
+ labibb->ibb_vreg.vreg_enabled = 1;
+ }
+ return 0;
+}
+
+static int qpnp_ibb_regulator_disable(struct regulator_dev *rdev)
+{
+ int rc;
+ struct qpnp_labibb *labibb = rdev_get_drvdata(rdev);
+
+ if (labibb->ibb_vreg.vreg_enabled && !labibb->swire_control) {
+
+ if (!labibb->standalone)
+ return qpnp_labibb_regulator_disable(labibb);
+
+ rc = qpnp_ibb_set_mode(labibb, IBB_SW_CONTROL_DIS);
+ if (rc < 0) {
+ pr_err("Unable to set IBB_MODULE_EN rc = %d\n", rc);
+ return rc;
+ }
+
+ labibb->ibb_vreg.vreg_enabled = 0;
+ }
+ return 0;
+}
+
+static int qpnp_ibb_regulator_is_enabled(struct regulator_dev *rdev)
+{
+ struct qpnp_labibb *labibb = rdev_get_drvdata(rdev);
+
+ if (labibb->swire_control)
+ return 0;
+
+ return labibb->ibb_vreg.vreg_enabled;
+}
+
+static int qpnp_ibb_regulator_set_voltage(struct regulator_dev *rdev,
+ int min_uV, int max_uV, unsigned int *selector)
+{
+ int rc = 0;
+
+ struct qpnp_labibb *labibb = rdev_get_drvdata(rdev);
+
+ if (labibb->swire_control)
+ return 0;
+
+ rc = labibb->ibb_ver_ops->set_voltage(labibb, min_uV, max_uV);
+ return rc;
+}
+
+
+static int qpnp_ibb_regulator_get_voltage(struct regulator_dev *rdev)
+{
+ struct qpnp_labibb *labibb = rdev_get_drvdata(rdev);
+
+ if (labibb->swire_control)
+ return 0;
+
+ return labibb->ibb_vreg.curr_volt;
+}
+
+static struct regulator_ops qpnp_ibb_ops = {
+ .enable = qpnp_ibb_regulator_enable,
+ .disable = qpnp_ibb_regulator_disable,
+ .is_enabled = qpnp_ibb_regulator_is_enabled,
+ .set_voltage = qpnp_ibb_regulator_set_voltage,
+ .get_voltage = qpnp_ibb_regulator_get_voltage,
+};
+
+static int register_qpnp_ibb_regulator(struct qpnp_labibb *labibb,
+ struct device_node *of_node)
+{
+ int rc = 0;
+ struct regulator_init_data *init_data;
+ struct regulator_desc *rdesc = &labibb->ibb_vreg.rdesc;
+ struct regulator_config cfg = {};
+ u8 val, ibb_enable_ctl, index;
+ u32 tmp;
+
+ if (!of_node) {
+ dev_err(labibb->dev, "qpnp ibb regulator device tree node is missing\n");
+ return -EINVAL;
+ }
+
+ init_data = of_get_regulator_init_data(labibb->dev, of_node, rdesc);
+ if (!init_data) {
+ pr_err("unable to get regulator init data for qpnp ibb regulator\n");
+ return -ENOMEM;
+ }
+
+ rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-min-voltage",
+ &(labibb->ibb_vreg.min_volt));
+ if (rc < 0) {
+ pr_err("qcom,qpnp-ibb-min-voltage is missing, rc = %d\n",
+ rc);
+ return rc;
+ }
+
+ rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-step-size",
+ &(labibb->ibb_vreg.step_size));
+ if (rc < 0) {
+ pr_err("qcom,qpnp-ibb-step-size is missing, rc = %d\n", rc);
+ return rc;
+ }
+
+ rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-slew-rate",
+ &(labibb->ibb_vreg.slew_rate));
+ if (rc < 0)
+ labibb->ibb_vreg.slew_rate = IBB_HW_DEFAULT_SLEW_RATE;
+
+ rc = labibb->ibb_ver_ops->soft_start_ctl(labibb, of_node);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_write register %x failed rc = %d\n",
+ REG_IBB_SOFT_START_CTL, rc);
+ return rc;
+ }
+
+ if (of_find_property(of_node, "qcom,output-voltage-one-pulse", NULL)) {
+ if (!labibb->swire_control) {
+ pr_err("output-voltage-one-pulse valid for SWIRE only\n");
+ return -EINVAL;
+ }
+ rc = of_property_read_u32(of_node,
+ "qcom,output-voltage-one-pulse", &tmp);
+ if (rc < 0) {
+ pr_err("failed to read qcom,output-voltage-one-pulse rc=%d\n",
+ rc);
+ return rc;
+ }
+ if (tmp > MAX_OUTPUT_PULSE_VOLTAGE_MV ||
+ tmp < MIN_OUTPUT_PULSE_VOLTAGE_MV) {
+ pr_err("Invalid one-pulse voltage range %d\n", tmp);
+ return -EINVAL;
+ }
+ rc = labibb->ibb_ver_ops->voltage_at_one_pulse(labibb, tmp);
+ if (rc < 0)
+ return rc;
+ }
+
+ rc = qpnp_labibb_read(labibb, labibb->ibb_base + REG_IBB_ENABLE_CTL,
+ &ibb_enable_ctl, 1);
+ if (rc < 0) {
+ pr_err("qpnp_ibb_read register %x failed rc = %d\n",
+ REG_IBB_ENABLE_CTL, rc);
+ return rc;
+ }
+
+ /*
+ * For pmi8998, override swire_control with what was configured
+ * before by the bootloader.
+ */
+ if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE)
+ labibb->swire_control = ibb_enable_ctl &
+ IBB_ENABLE_CTL_SWIRE_RDY;
+
+ if (ibb_enable_ctl &
+ (IBB_ENABLE_CTL_SWIRE_RDY | IBB_ENABLE_CTL_MODULE_EN)) {
+
+ rc = labibb->ibb_ver_ops->get_mode(labibb);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_read register %x failed rc = %d\n",
+ REG_IBB_LCD_AMOLED_SEL, rc);
+ return rc;
+ }
+ rc = qpnp_labibb_read(labibb, labibb->ibb_base +
+ REG_IBB_VOLTAGE, &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_read read register %x failed rc = %d\n",
+ REG_IBB_VOLTAGE, rc);
+ return rc;
+ }
+
+ labibb->ibb_vreg.curr_volt =
+ (val & IBB_VOLTAGE_SET_MASK) *
+ labibb->ibb_vreg.step_size +
+ labibb->ibb_vreg.min_volt;
+
+ if (labibb->mode == QPNP_LABIBB_LCD_MODE) {
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-ibb-init-lcd-voltage",
+ &(labibb->ibb_vreg.curr_volt));
+ if (rc < 0) {
+ pr_err("get qcom,qpnp-ibb-init-lcd-voltage failed, rc = %d\n",
+ rc);
+ return rc;
+ }
+ } else if (!(val & IBB_VOLTAGE_OVERRIDE_EN)) {
+ rc = of_property_read_u32(of_node,
+ "qcom,qpnp-ibb-init-amoled-voltage",
+ &(labibb->ibb_vreg.curr_volt));
+ if (rc < 0) {
+ pr_err("get qcom,qpnp-ibb-init-amoled-voltage failed, rc = %d\n",
+ rc);
+ return rc;
+ }
+
+ }
+
+ rc = qpnp_labibb_read(labibb, labibb->ibb_base +
+ REG_IBB_PWRUP_PWRDN_CTL_1, &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_config_init read register %x failed rc = %d\n",
+ REG_IBB_PWRUP_PWRDN_CTL_1, rc);
+ return rc;
+ }
+
+ index = (val & IBB_PWRUP_PWRDN_CTL_1_DLY1_MASK) >>
+ IBB_PWRUP_PWRDN_CTL_1_DLY1_SHIFT;
+ labibb->ibb_vreg.pwrup_dly = ibb_pwrup_dly_table[index];
+ index = val & IBB_PWRUP_PWRDN_CTL_1_DLY2_MASK;
+ labibb->ibb_vreg.pwrdn_dly = ibb_pwrdn_dly_table[index];
+
+ labibb->ibb_vreg.vreg_enabled = 1;
+ } else {
+ /* SWIRE_RDY and IBB_MODULE_EN not enabled */
+ rc = qpnp_ibb_dt_init(labibb, of_node);
+ if (rc < 0) {
+ pr_err("qpnp-ibb: wrong DT parameter specified: rc = %d\n",
+ rc);
+ return rc;
+ }
+ }
+
+ if (labibb->mode == QPNP_LABIBB_AMOLED_MODE &&
+ qpnp_ibb_poff_ctl_required(labibb)) {
+
+ val = IBB_OVERRIDE_NONOVERLAP | IBB_NFET_GATE_DELAY_2;
+ rc = qpnp_labibb_sec_masked_write(labibb, labibb->ibb_base,
+ REG_IBB_NONOVERLAP_TIME_1,
+ IBB_OVERRIDE_NONOVERLAP | IBB_NONOVERLAP_NFET_MASK,
+ val);
+
+ if (rc < 0) {
+ pr_err("qpnp_labibb_sec_masked_write register %x failed rc = %d\n",
+ REG_IBB_NONOVERLAP_TIME_1, rc);
+ return rc;
+ }
+
+ val = IBB_N2P_MUX_SEL;
+ rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base,
+ REG_IBB_NONOVERLAP_TIME_2, val);
+
+ if (rc < 0) {
+ pr_err("qpnp_labibb_sec_write register %x failed rc = %d\n",
+ REG_IBB_NONOVERLAP_TIME_2, rc);
+ return rc;
+ }
+
+ val = IBB_FASTER_PFET_OFF;
+ rc = qpnp_labibb_masked_write(labibb,
+ labibb->ibb_base + REG_IBB_SPARE_CTL,
+ IBB_POFF_CTL_MASK, val);
+ if (rc < 0) {
+ pr_err("write to register %x failed rc = %d\n",
+ REG_IBB_SPARE_CTL, rc);
+ return rc;
+ }
+ }
+
+ if (labibb->standalone) {
+ val = 0;
+ rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base,
+ REG_IBB_PWRUP_PWRDN_CTL_1, val);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_sec_write register %x failed rc = %d\n",
+ REG_IBB_PWRUP_PWRDN_CTL_1, rc);
+ return rc;
+ }
+ labibb->ibb_vreg.pwrup_dly = 0;
+ labibb->ibb_vreg.pwrdn_dly = 0;
+ }
+
+ rc = qpnp_labibb_read(labibb, labibb->ibb_base + REG_IBB_MODULE_RDY,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_ibb_read read register %x failed rc = %d\n",
+ REG_IBB_MODULE_RDY, rc);
+ return rc;
+ }
+
+ if (!(val & IBB_MODULE_RDY_EN)) {
+ val = IBB_MODULE_RDY_EN;
+
+ rc = qpnp_labibb_write(labibb, labibb->ibb_base +
+ REG_IBB_MODULE_RDY, &val, 1);
+
+ if (rc < 0) {
+ pr_err("qpnp_ibb_dt_init write register %x failed rc = %d\n",
+ REG_IBB_MODULE_RDY, rc);
+ return rc;
+ }
+ }
+
+ if (of_property_read_bool(of_node,
+ "qcom,qpnp-ibb-enable-pfm-mode")) {
+ rc = qpnp_ibb_pfm_mode_enable(labibb, of_node);
+ if (rc < 0)
+ return rc;
+ }
+
+ if (labibb->pbs_control) {
+ rc = qpnp_labibb_pbs_mode_enable(labibb, of_node);
+ if (rc < 0)
+ return rc;
+ }
+
+ if (init_data->constraints.name) {
+ rdesc->owner = THIS_MODULE;
+ rdesc->type = REGULATOR_VOLTAGE;
+ rdesc->ops = &qpnp_ibb_ops;
+ rdesc->name = init_data->constraints.name;
+
+ cfg.dev = labibb->dev;
+ cfg.init_data = init_data;
+ cfg.driver_data = labibb;
+ cfg.of_node = of_node;
+
+ if (of_get_property(labibb->dev->of_node, "parent-supply",
+ NULL))
+ init_data->supply_regulator = "parent";
+
+ init_data->constraints.valid_ops_mask
+ |= REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS;
+
+ labibb->ibb_vreg.rdev = regulator_register(rdesc, &cfg);
+ if (IS_ERR(labibb->ibb_vreg.rdev)) {
+ rc = PTR_ERR(labibb->ibb_vreg.rdev);
+ labibb->ibb_vreg.rdev = NULL;
+ pr_err("unable to get regulator init data for qpnp ibb regulator, rc = %d\n",
+ rc);
+
+ return rc;
+ }
+ } else {
+ dev_err(labibb->dev, "qpnp ibb regulator name missing\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int qpnp_lab_register_irq(struct device_node *child,
+ struct qpnp_labibb *labibb)
+{
+ if (is_lab_vreg_ok_irq_available(labibb)) {
+ labibb->lab_vreg.lab_vreg_ok_irq =
+ of_irq_get_byname(child, "lab-vreg-ok");
+ if (labibb->lab_vreg.lab_vreg_ok_irq < 0) {
+ pr_err("Invalid lab-vreg-ok irq\n");
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+static int qpnp_labibb_check_ttw_supported(struct qpnp_labibb *labibb)
+{
+ int rc = 0;
+ u8 val;
+
+ switch (labibb->pmic_rev_id->pmic_subtype) {
+ case PMI8996_SUBTYPE:
+ rc = qpnp_labibb_read(labibb, labibb->ibb_base +
+ REG_IBB_REVISION4, &val, 1);
+ if (rc < 0) {
+ pr_err("qpnp_labibb_read register %x failed rc = %d\n",
+ REG_IBB_REVISION4, rc);
+ return rc;
+ }
+
+ /* PMI8996 has revision 1 */
+ if (val < 1) {
+ pr_err("TTW feature cannot be enabled for revision %d\n",
+ val);
+ labibb->ttw_en = false;
+ }
+ /* FORCE_LAB_ON in TTW is not required for PMI8996 */
+ labibb->ttw_force_lab_on = false;
+ break;
+ case PMI8950_SUBTYPE:
+ /* TTW supported for all revisions */
+ break;
+ default:
+ pr_info("TTW mode not supported for PMIC-subtype = %d\n",
+ labibb->pmic_rev_id->pmic_subtype);
+ labibb->ttw_en = false;
+ break;
+
+ }
+ return rc;
+}
+
+static int qpnp_labibb_regulator_probe(struct platform_device *pdev)
+{
+ struct qpnp_labibb *labibb;
+ unsigned int base;
+ struct device_node *child, *revid_dev_node;
+ const char *mode_name;
+ u8 type, revision;
+ int rc = 0;
+
+ labibb = devm_kzalloc(&pdev->dev, sizeof(*labibb), GFP_KERNEL);
+ if (labibb == NULL)
+ return -ENOMEM;
+
+ labibb->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (!labibb->regmap) {
+ dev_err(&pdev->dev, "Couldn't get parent's regmap\n");
+ return -EINVAL;
+ }
+
+ labibb->dev = &(pdev->dev);
+ labibb->pdev = pdev;
+
+ mutex_init(&(labibb->lab_vreg.lab_mutex));
+ mutex_init(&(labibb->ibb_vreg.ibb_mutex));
+ mutex_init(&(labibb->bus_mutex));
+
+ revid_dev_node = of_parse_phandle(labibb->dev->of_node,
+ "qcom,pmic-revid", 0);
+ if (!revid_dev_node) {
+ pr_err("Missing qcom,pmic-revid property - driver failed\n");
+ return -EINVAL;
+ }
+
+ labibb->pmic_rev_id = get_revid_data(revid_dev_node);
+ if (IS_ERR(labibb->pmic_rev_id)) {
+ pr_debug("Unable to get revid data\n");
+ return -EPROBE_DEFER;
+ }
+
+ if (labibb->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) {
+ labibb->ibb_ver_ops = &ibb_ops_v2;
+ labibb->lab_ver_ops = &lab_ops_v2;
+ } else {
+ labibb->ibb_ver_ops = &ibb_ops_v1;
+ labibb->lab_ver_ops = &lab_ops_v1;
+ }
+
+ if (labibb->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) {
+ labibb->mode = QPNP_LABIBB_AMOLED_MODE;
+ } else {
+ rc = of_property_read_string(labibb->dev->of_node,
+ "qcom,qpnp-labibb-mode", &mode_name);
+ if (!rc) {
+ if (strcmp("lcd", mode_name) == 0) {
+ labibb->mode = QPNP_LABIBB_LCD_MODE;
+ } else if (strcmp("amoled", mode_name) == 0) {
+ labibb->mode = QPNP_LABIBB_AMOLED_MODE;
+ } else {
+ pr_err("Invalid device property in qcom,qpnp-labibb-mode: %s\n",
+ mode_name);
+ return -EINVAL;
+ }
+ } else {
+ pr_err("qpnp_labibb: qcom,qpnp-labibb-mode is missing.\n");
+ return rc;
+ }
+ }
+
+ labibb->standalone = of_property_read_bool(labibb->dev->of_node,
+ "qcom,labibb-standalone");
+
+ labibb->ttw_en = of_property_read_bool(labibb->dev->of_node,
+ "qcom,labibb-touch-to-wake-en");
+ if (labibb->ttw_en && labibb->mode != QPNP_LABIBB_LCD_MODE) {
+ pr_err("Invalid mode for TTW\n");
+ return -EINVAL;
+ }
+
+ labibb->ttw_force_lab_on = of_property_read_bool(
+ labibb->dev->of_node, "qcom,labibb-ttw-force-lab-on");
+
+ labibb->swire_control = of_property_read_bool(labibb->dev->of_node,
+ "qcom,swire-control");
+
+ labibb->pbs_control = of_property_read_bool(labibb->dev->of_node,
+ "qcom,pbs-control");
+ if (labibb->swire_control && labibb->mode != QPNP_LABIBB_AMOLED_MODE) {
+ pr_err("Invalid mode for SWIRE control\n");
+ return -EINVAL;
+ }
+
+ if (labibb->swire_control) {
+ labibb->skip_2nd_swire_cmd =
+ of_property_read_bool(labibb->dev->of_node,
+ "qcom,skip-2nd-swire-cmd");
+
+ rc = of_property_read_u32(labibb->dev->of_node,
+ "qcom,swire-2nd-cmd-delay",
+ &labibb->swire_2nd_cmd_delay);
+ if (rc < 0)
+ labibb->swire_2nd_cmd_delay =
+ SWIRE_DEFAULT_2ND_CMD_DLY_MS;
+
+ rc = of_property_read_u32(labibb->dev->of_node,
+ "qcom,swire-ibb-ps-enable-delay",
+ &labibb->swire_ibb_ps_enable_delay);
+ if (rc < 0)
+ labibb->swire_ibb_ps_enable_delay =
+ SWIRE_DEFAULT_IBB_PS_ENABLE_DLY_MS;
+ }
+
+ if (of_get_available_child_count(pdev->dev.of_node) == 0) {
+ pr_err("no child nodes\n");
+ return -ENXIO;
+ }
+
+ for_each_available_child_of_node(pdev->dev.of_node, child) {
+ rc = of_property_read_u32(child, "reg", &base);
+ if (rc < 0) {
+ dev_err(&pdev->dev,
+ "Couldn't find reg in node = %s rc = %d\n",
+ child->full_name, rc);
+ return rc;
+ }
+
+ rc = qpnp_labibb_read(labibb, base + REG_REVISION_2,
+ &revision, 1);
+ if (rc < 0) {
+ pr_err("Reading REVISION_2 failed rc=%d\n", rc);
+ goto fail_registration;
+ }
+
+ rc = qpnp_labibb_read(labibb, base + REG_PERPH_TYPE,
+ &type, 1);
+ if (rc < 0) {
+ pr_err("Peripheral type read failed rc=%d\n", rc);
+ goto fail_registration;
+ }
+
+ switch (type) {
+ case QPNP_LAB_TYPE:
+ labibb->lab_base = base;
+ labibb->lab_dig_major = revision;
+ rc = qpnp_lab_register_irq(child, labibb);
+ if (rc) {
+ pr_err("Failed to register LAB IRQ rc=%d\n",
+ rc);
+ goto fail_registration;
+ }
+ rc = register_qpnp_lab_regulator(labibb, child);
+ if (rc < 0)
+ goto fail_registration;
+ break;
+
+ case QPNP_IBB_TYPE:
+ labibb->ibb_base = base;
+ labibb->ibb_dig_major = revision;
+ rc = register_qpnp_ibb_regulator(labibb, child);
+ if (rc < 0)
+ goto fail_registration;
+ break;
+
+ default:
+ pr_err("qpnp_labibb: unknown peripheral type %x\n",
+ type);
+ rc = -EINVAL;
+ goto fail_registration;
+ }
+ }
+
+ if (labibb->ttw_en) {
+ rc = qpnp_labibb_check_ttw_supported(labibb);
+ if (rc < 0) {
+ pr_err("pmic revision check failed for TTW rc=%d\n",
+ rc);
+ goto fail_registration;
+ }
+ }
+ dev_set_drvdata(&pdev->dev, labibb);
+ pr_info("LAB/IBB registered successfully, lab_vreg enable=%d ibb_vreg enable=%d swire_control=%d\n",
+ labibb->lab_vreg.vreg_enabled,
+ labibb->ibb_vreg.vreg_enabled,
+ labibb->swire_control);
+
+ return 0;
+
+fail_registration:
+ if (labibb->lab_vreg.rdev)
+ regulator_unregister(labibb->lab_vreg.rdev);
+ if (labibb->ibb_vreg.rdev)
+ regulator_unregister(labibb->ibb_vreg.rdev);
+
+ return rc;
+}
+
+static int qpnp_labibb_regulator_remove(struct platform_device *pdev)
+{
+ struct qpnp_labibb *labibb = dev_get_drvdata(&pdev->dev);
+
+ if (labibb) {
+ if (labibb->lab_vreg.rdev)
+ regulator_unregister(labibb->lab_vreg.rdev);
+ if (labibb->ibb_vreg.rdev)
+ regulator_unregister(labibb->ibb_vreg.rdev);
+ }
+ return 0;
+}
+
+static const struct of_device_id spmi_match_table[] = {
+ { .compatible = QPNP_LABIBB_REGULATOR_DRIVER_NAME, },
+ { },
+};
+
+static struct platform_driver qpnp_labibb_regulator_driver = {
+ .driver = {
+ .name = QPNP_LABIBB_REGULATOR_DRIVER_NAME,
+ .of_match_table = spmi_match_table,
+ },
+ .probe = qpnp_labibb_regulator_probe,
+ .remove = qpnp_labibb_regulator_remove,
+};
+
+static int __init qpnp_labibb_regulator_init(void)
+{
+ return platform_driver_register(&qpnp_labibb_regulator_driver);
+}
+arch_initcall(qpnp_labibb_regulator_init);
+
+static void __exit qpnp_labibb_regulator_exit(void)
+{
+ platform_driver_unregister(&qpnp_labibb_regulator_driver);
+}
+module_exit(qpnp_labibb_regulator_exit);
+
+MODULE_DESCRIPTION("QPNP labibb driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/regulator/qpnp-lcdb-regulator.c b/drivers/regulator/qpnp-lcdb-regulator.c
new file mode 100644
index 0000000..a08ade6
--- /dev/null
+++ b/drivers/regulator/qpnp-lcdb-regulator.c
@@ -0,0 +1,1692 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "LCDB: %s: " fmt, __func__
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/regulator/machine.h>
+
+#define QPNP_LCDB_REGULATOR_DRIVER_NAME "qcom,qpnp-lcdb-regulator"
+
+/* LCDB */
+#define LCDB_STS1_REG 0x08
+
+#define INT_RT_STATUS_REG 0x10
+#define VREG_OK_RT_STS_BIT BIT(0)
+
+#define LCDB_AUTO_TOUCH_WAKE_CTL_REG 0x40
+#define EN_AUTO_TOUCH_WAKE_BIT BIT(7)
+#define ATTW_TOFF_TIME_MASK GENMASK(3, 2)
+#define ATTW_TON_TIME_MASK GENMASK(1, 0)
+#define ATTW_TOFF_TIME_SHIFT 2
+#define ATTW_MIN_MS 4
+#define ATTW_MAX_MS 32
+
+#define LCDB_BST_OUTPUT_VOLTAGE_REG 0x41
+
+#define LCDB_MODULE_RDY_REG 0x45
+#define MODULE_RDY_BIT BIT(7)
+
+#define LCDB_ENABLE_CTL1_REG 0x46
+#define MODULE_EN_BIT BIT(7)
+#define HWEN_RDY_BIT BIT(6)
+
+/* BST */
+#define LCDB_BST_PD_CTL_REG 0x47
+#define BOOST_DIS_PULLDOWN_BIT BIT(1)
+#define BOOST_PD_STRENGTH_BIT BIT(0)
+
+#define LCDB_BST_ILIM_CTL_REG 0x4B
+#define EN_BST_ILIM_BIT BIT(7)
+#define SET_BST_ILIM_MASK GENMASK(2, 0)
+#define MIN_BST_ILIM_MA 200
+#define MAX_BST_ILIM_MA 1600
+
+#define LCDB_PS_CTL_REG 0x50
+#define EN_PS_BIT BIT(7)
+#define PS_THRESHOLD_MASK GENMASK(1, 0)
+#define MIN_BST_PS_MA 50
+#define MAX_BST_PS_MA 80
+
+#define LCDB_RDSON_MGMNT_REG 0x53
+#define NFET_SW_SIZE_MASK GENMASK(3, 2)
+#define NFET_SW_SIZE_SHIFT 2
+#define PFET_SW_SIZE_MASK GENMASK(1, 0)
+
+#define LCDB_BST_VREG_OK_CTL_REG 0x55
+#define BST_VREG_OK_DEB_MASK GENMASK(1, 0)
+
+#define LCDB_SOFT_START_CTL_REG 0x5F
+
+#define LCDB_MISC_CTL_REG 0x60
+#define AUTO_GM_EN_BIT BIT(4)
+#define EN_TOUCH_WAKE_BIT BIT(3)
+#define DIS_SCP_BIT BIT(0)
+
+#define LCDB_PFM_CTL_REG 0x62
+#define EN_PFM_BIT BIT(7)
+#define BYP_BST_SOFT_START_COMP_BIT BIT(0)
+#define PFM_HYSTERESIS_SHIFT 4
+#define PFM_CURRENT_SHIFT 2
+
+#define LCDB_PWRUP_PWRDN_CTL_REG 0x66
+
+/* LDO */
+#define LCDB_LDO_OUTPUT_VOLTAGE_REG 0x71
+#define SET_OUTPUT_VOLTAGE_MASK GENMASK(4, 0)
+
+#define LCDB_LDO_VREG_OK_CTL_REG 0x75
+#define VREG_OK_DEB_MASK GENMASK(1, 0)
+
+#define LCDB_LDO_PD_CTL_REG 0x77
+#define LDO_DIS_PULLDOWN_BIT BIT(1)
+#define LDO_PD_STRENGTH_BIT BIT(0)
+
+#define LCDB_LDO_ILIM_CTL1_REG 0x7B
+#define EN_LDO_ILIM_BIT BIT(7)
+#define SET_LDO_ILIM_MASK GENMASK(2, 0)
+#define MIN_LDO_ILIM_MA 110
+#define MAX_LDO_ILIM_MA 460
+#define LDO_ILIM_STEP_MA 50
+
+#define LCDB_LDO_ILIM_CTL2_REG 0x7C
+
+#define LCDB_LDO_SOFT_START_CTL_REG 0x7F
+#define SOFT_START_MASK GENMASK(1, 0)
+
+/* NCP */
+#define LCDB_NCP_OUTPUT_VOLTAGE_REG 0x81
+
+#define LCDB_NCP_VREG_OK_CTL_REG 0x85
+
+#define LCDB_NCP_PD_CTL_REG 0x87
+#define NCP_DIS_PULLDOWN_BIT BIT(1)
+#define NCP_PD_STRENGTH_BIT BIT(0)
+
+#define LCDB_NCP_ILIM_CTL1_REG 0x8B
+#define EN_NCP_ILIM_BIT BIT(7)
+#define SET_NCP_ILIM_MASK GENMASK(1, 0)
+#define MIN_NCP_ILIM_MA 260
+#define MAX_NCP_ILIM_MA 810
+
+#define LCDB_NCP_ILIM_CTL2_REG 0x8C
+
+#define LCDB_NCP_SOFT_START_CTL_REG 0x8F
+
+/* common for BST/NCP/LDO */
+#define MIN_DBC_US 2
+#define MAX_DBC_US 32
+
+#define MIN_SOFT_START_US 0
+#define MAX_SOFT_START_US 2000
+
+struct ldo_regulator {
+ struct regulator_desc rdesc;
+ struct regulator_dev *rdev;
+ struct device_node *node;
+
+ /* LDO DT params */
+ int pd;
+ int pd_strength;
+ int ilim_ma;
+ int soft_start_us;
+ int vreg_ok_dbc_us;
+ int voltage_mv;
+};
+
+struct ncp_regulator {
+ struct regulator_desc rdesc;
+ struct regulator_dev *rdev;
+ struct device_node *node;
+
+ /* NCP DT params */
+ int pd;
+ int pd_strength;
+ int ilim_ma;
+ int soft_start_us;
+ int vreg_ok_dbc_us;
+ int voltage_mv;
+};
+
+struct bst_params {
+ struct device_node *node;
+
+ /* BST DT params */
+ int pd;
+ int pd_strength;
+ int ilim_ma;
+ int ps;
+ int ps_threshold;
+ int soft_start_us;
+ int vreg_ok_dbc_us;
+ int voltage_mv;
+};
+
+struct qpnp_lcdb {
+ struct device *dev;
+ struct platform_device *pdev;
+ struct regmap *regmap;
+ u32 base;
+
+ /* TTW params */
+ bool ttw_enable;
+ bool ttw_mode_sw;
+
+ /* status parameters */
+ bool lcdb_enabled;
+ bool settings_saved;
+
+ struct mutex lcdb_mutex;
+ struct mutex read_write_mutex;
+ struct bst_params bst;
+ struct ldo_regulator ldo;
+ struct ncp_regulator ncp;
+};
+
+struct settings {
+ u16 address;
+ u8 value;
+ bool sec_access;
+};
+
+enum lcdb_module {
+ LDO,
+ NCP,
+ BST,
+};
+
+enum pfm_hysteresis {
+ PFM_HYST_15MV,
+ PFM_HYST_25MV,
+ PFM_HYST_35MV,
+ PFM_HYST_45MV,
+};
+
+enum pfm_peak_current {
+ PFM_PEAK_CURRENT_300MA,
+ PFM_PEAK_CURRENT_400MA,
+ PFM_PEAK_CURRENT_500MA,
+ PFM_PEAK_CURRENT_600MA,
+};
+
+enum rdson_fet_size {
+ RDSON_QUARTER,
+ RDSON_HALF,
+ RDSON_THREE_FOURTH,
+ RDSON_FULLSIZE,
+};
+
+enum lcdb_settings_index {
+ LCDB_BST_PD_CTL = 0,
+ LCDB_RDSON_MGMNT,
+ LCDB_MISC_CTL,
+ LCDB_SOFT_START_CTL,
+ LCDB_PFM_CTL,
+ LCDB_PWRUP_PWRDN_CTL,
+ LCDB_LDO_PD_CTL,
+ LCDB_LDO_SOFT_START_CTL,
+ LCDB_NCP_PD_CTL,
+ LCDB_NCP_SOFT_START_CTL,
+ LCDB_SETTING_MAX,
+};
+
+static u32 soft_start_us[] = {
+ 0,
+ 500,
+ 1000,
+ 2000,
+};
+
+static u32 dbc_us[] = {
+ 2,
+ 4,
+ 16,
+ 32,
+};
+
+static u32 ncp_ilim_ma[] = {
+ 260,
+ 460,
+ 640,
+ 810,
+};
+
+#define SETTING(_id, _sec_access) \
+ [_id] = { \
+ .address = _id##_REG, \
+ .sec_access = _sec_access, \
+ } \
+
+static bool is_between(int value, int min, int max)
+{
+ if (value < min || value > max)
+ return false;
+ return true;
+}
+
+static int qpnp_lcdb_read(struct qpnp_lcdb *lcdb,
+ u16 addr, u8 *value, u8 count)
+{
+ int rc = 0;
+
+ mutex_lock(&lcdb->read_write_mutex);
+ rc = regmap_bulk_read(lcdb->regmap, addr, value, count);
+ if (rc < 0)
+ pr_err("Failed to read from addr=0x%02x rc=%d\n", addr, rc);
+ mutex_unlock(&lcdb->read_write_mutex);
+
+ return rc;
+}
+
+static int qpnp_lcdb_write(struct qpnp_lcdb *lcdb,
+ u16 addr, u8 *value, u8 count)
+{
+ int rc;
+
+ mutex_lock(&lcdb->read_write_mutex);
+ rc = regmap_bulk_write(lcdb->regmap, addr, value, count);
+ if (rc < 0)
+ pr_err("Failed to write to addr=0x%02x rc=%d\n", addr, rc);
+ mutex_unlock(&lcdb->read_write_mutex);
+
+ return rc;
+}
+
+#define SEC_ADDRESS_REG 0xD0
+#define SECURE_UNLOCK_VALUE 0xA5
+static int qpnp_lcdb_secure_write(struct qpnp_lcdb *lcdb,
+ u16 addr, u8 value)
+{
+ int rc;
+ u8 val = SECURE_UNLOCK_VALUE;
+
+ mutex_lock(&lcdb->read_write_mutex);
+ rc = regmap_write(lcdb->regmap, lcdb->base + SEC_ADDRESS_REG, val);
+ if (rc < 0) {
+ pr_err("Failed to unlock register rc=%d\n", rc);
+ goto fail_write;
+ }
+ rc = regmap_write(lcdb->regmap, addr, value);
+ if (rc < 0)
+ pr_err("Failed to write to addr=0x%02x rc=%d\n", addr, rc);
+
+fail_write:
+ mutex_unlock(&lcdb->read_write_mutex);
+ return rc;
+}
+
+static int qpnp_lcdb_masked_write(struct qpnp_lcdb *lcdb,
+ u16 addr, u8 mask, u8 value)
+{
+ int rc = 0;
+
+ mutex_lock(&lcdb->read_write_mutex);
+ rc = regmap_update_bits(lcdb->regmap, addr, mask, value);
+ if (rc < 0)
+ pr_err("Failed to write addr=0x%02x value=0x%02x rc=%d\n",
+ addr, value, rc);
+ mutex_unlock(&lcdb->read_write_mutex);
+
+ return rc;
+}
+
+static bool is_lcdb_enabled(struct qpnp_lcdb *lcdb)
+{
+ int rc;
+ u8 val = 0;
+
+ rc = qpnp_lcdb_read(lcdb, lcdb->base + LCDB_ENABLE_CTL1_REG, &val, 1);
+ if (rc < 0)
+ pr_err("Failed to read ENABLE_CTL1 rc=%d\n", rc);
+
+ return rc ? false : !!(val & MODULE_EN_BIT);
+}
+
+static int dump_status_registers(struct qpnp_lcdb *lcdb)
+{
+ int rc = 0;
+ u8 sts[6] = {0};
+
+ rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_STS1_REG, &sts[0], 6);
+ if (rc < 0) {
+ pr_err("Failed to write to STS registers rc=%d\n", rc);
+ } else {
+ rc = qpnp_lcdb_read(lcdb, lcdb->base + LCDB_STS1_REG, sts, 6);
+ if (rc < 0)
+ pr_err("Failed to read lcdb status rc=%d\n", rc);
+ else
+ pr_err("STS1=0x%02x STS2=0x%02x STS3=0x%02x STS4=0x%02x STS5=0x%02x, STS6=0x%02x\n",
+ sts[0], sts[1], sts[2], sts[3], sts[4], sts[5]);
+ }
+
+ return rc;
+}
+
+static struct settings lcdb_settings[] = {
+ SETTING(LCDB_BST_PD_CTL, false),
+ SETTING(LCDB_RDSON_MGMNT, false),
+ SETTING(LCDB_MISC_CTL, false),
+ SETTING(LCDB_SOFT_START_CTL, false),
+ SETTING(LCDB_PFM_CTL, false),
+ SETTING(LCDB_PWRUP_PWRDN_CTL, true),
+ SETTING(LCDB_LDO_PD_CTL, false),
+ SETTING(LCDB_LDO_SOFT_START_CTL, false),
+ SETTING(LCDB_NCP_PD_CTL, false),
+ SETTING(LCDB_NCP_SOFT_START_CTL, false),
+};
+
+static int qpnp_lcdb_save_settings(struct qpnp_lcdb *lcdb)
+{
+ int i, rc = 0;
+
+ for (i = 0; i < ARRAY_SIZE(lcdb_settings); i++) {
+ rc = qpnp_lcdb_read(lcdb, lcdb->base +
+ lcdb_settings[i].address,
+ &lcdb_settings[i].value, 1);
+ if (rc < 0) {
+ pr_err("Failed to read lcdb register address=%x\n",
+ lcdb_settings[i].address);
+ return rc;
+ }
+ }
+
+ return rc;
+}
+
+static int qpnp_lcdb_restore_settings(struct qpnp_lcdb *lcdb)
+{
+ int i, rc = 0;
+
+ for (i = 0; i < ARRAY_SIZE(lcdb_settings); i++) {
+ if (lcdb_settings[i].sec_access)
+ rc = qpnp_lcdb_secure_write(lcdb, lcdb->base +
+ lcdb_settings[i].address,
+ lcdb_settings[i].value);
+ else
+ rc = qpnp_lcdb_write(lcdb, lcdb->base +
+ lcdb_settings[i].address,
+ &lcdb_settings[i].value, 1);
+ if (rc < 0) {
+ pr_err("Failed to write register address=%x\n",
+ lcdb_settings[i].address);
+ return rc;
+ }
+ }
+
+ return rc;
+}
+
+static int qpnp_lcdb_ttw_enter(struct qpnp_lcdb *lcdb)
+{
+ int rc;
+ u8 val;
+
+ if (!lcdb->settings_saved) {
+ rc = qpnp_lcdb_save_settings(lcdb);
+ if (rc < 0) {
+ pr_err("Failed to save LCDB settings rc=%d\n", rc);
+ return rc;
+ }
+ lcdb->settings_saved = true;
+ }
+
+ val = BOOST_DIS_PULLDOWN_BIT;
+ rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_BST_PD_CTL_REG,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to set BST PD rc=%d\n", rc);
+ return rc;
+ }
+
+ val = (RDSON_HALF << NFET_SW_SIZE_SHIFT) | RDSON_HALF;
+ rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_RDSON_MGMNT_REG,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to set RDSON MGMT rc=%d\n", rc);
+ return rc;
+ }
+
+ val = AUTO_GM_EN_BIT | EN_TOUCH_WAKE_BIT | DIS_SCP_BIT;
+ rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_MISC_CTL_REG,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to set MISC CTL rc=%d\n", rc);
+ return rc;
+ }
+
+ val = 0;
+ rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_SOFT_START_CTL_REG,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to set LCDB_SOFT_START rc=%d\n", rc);
+ return rc;
+ }
+
+ val = EN_PFM_BIT | (PFM_HYST_25MV << PFM_HYSTERESIS_SHIFT) |
+ (PFM_PEAK_CURRENT_400MA << PFM_CURRENT_SHIFT) |
+ BYP_BST_SOFT_START_COMP_BIT;
+ rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_PFM_CTL_REG,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to set PFM_CTL rc=%d\n", rc);
+ return rc;
+ }
+
+ val = 0;
+ rc = qpnp_lcdb_secure_write(lcdb, lcdb->base + LCDB_PWRUP_PWRDN_CTL_REG,
+ val);
+ if (rc < 0) {
+ pr_err("Failed to set PWRUP_PWRDN_CTL rc=%d\n", rc);
+ return rc;
+ }
+
+ val = LDO_DIS_PULLDOWN_BIT;
+ rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_LDO_PD_CTL_REG,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to set LDO_PD_CTL rc=%d\n", rc);
+ return rc;
+ }
+
+ val = 0;
+ rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_LDO_SOFT_START_CTL_REG,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to set LDO_SOFT_START rc=%d\n", rc);
+ return rc;
+ }
+
+ val = NCP_DIS_PULLDOWN_BIT;
+ rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_NCP_PD_CTL_REG,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to set NCP_PD_CTL rc=%d\n", rc);
+ return rc;
+ }
+
+ val = 0;
+ rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_NCP_SOFT_START_CTL_REG,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to set NCP_SOFT_START rc=%d\n", rc);
+ return rc;
+ }
+
+ if (lcdb->ttw_mode_sw) {
+ rc = qpnp_lcdb_masked_write(lcdb, lcdb->base +
+ LCDB_AUTO_TOUCH_WAKE_CTL_REG,
+ EN_AUTO_TOUCH_WAKE_BIT,
+ EN_AUTO_TOUCH_WAKE_BIT);
+ if (rc < 0)
+ pr_err("Failed to enable auto(sw) TTW\n rc = %d\n", rc);
+ } else {
+ val = HWEN_RDY_BIT;
+ rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_ENABLE_CTL1_REG,
+ &val, 1);
+ if (rc < 0)
+ pr_err("Failed to hw_enable lcdb rc= %d\n", rc);
+ }
+
+ return rc;
+}
+
+static int qpnp_lcdb_ttw_exit(struct qpnp_lcdb *lcdb)
+{
+ int rc;
+
+ if (lcdb->settings_saved) {
+ rc = qpnp_lcdb_restore_settings(lcdb);
+ if (rc < 0) {
+ pr_err("Failed to restore lcdb settings rc=%d\n", rc);
+ return rc;
+ }
+ lcdb->settings_saved = false;
+ }
+
+ return 0;
+}
+
+static int qpnp_lcdb_enable(struct qpnp_lcdb *lcdb)
+{
+ int rc = 0, timeout, delay;
+ u8 val = 0;
+
+ if (lcdb->lcdb_enabled)
+ return 0;
+
+ if (lcdb->ttw_enable) {
+ rc = qpnp_lcdb_ttw_exit(lcdb);
+ if (rc < 0) {
+ pr_err("Failed to exit TTW mode rc=%d\n", rc);
+ return rc;
+ }
+ }
+
+ val = MODULE_EN_BIT;
+ rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_ENABLE_CTL1_REG,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to enable lcdb rc= %d\n", rc);
+ goto fail_enable;
+ }
+
+ /* poll for vreg_ok */
+ timeout = 10;
+ delay = lcdb->bst.soft_start_us + lcdb->ldo.soft_start_us +
+ lcdb->ncp.soft_start_us;
+ delay += lcdb->bst.vreg_ok_dbc_us + lcdb->ldo.vreg_ok_dbc_us +
+ lcdb->ncp.vreg_ok_dbc_us;
+ while (timeout--) {
+ rc = qpnp_lcdb_read(lcdb, lcdb->base + INT_RT_STATUS_REG,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to poll for vreg-ok status rc=%d\n", rc);
+ break;
+ }
+ if (val & VREG_OK_RT_STS_BIT)
+ break;
+
+ usleep_range(delay, delay + 100);
+ }
+
+ if (rc || !timeout) {
+ if (!timeout) {
+ pr_err("lcdb-vreg-ok status failed to change\n");
+ rc = -ETIMEDOUT;
+ }
+ goto fail_enable;
+ }
+
+ lcdb->lcdb_enabled = true;
+ pr_debug("lcdb enabled successfully!\n");
+
+ return 0;
+
+fail_enable:
+ dump_status_registers(lcdb);
+ pr_err("Failed to enable lcdb rc=%d\n", rc);
+ return rc;
+}
+
+static int qpnp_lcdb_disable(struct qpnp_lcdb *lcdb)
+{
+ int rc = 0;
+ u8 val;
+
+ if (!lcdb->lcdb_enabled)
+ return 0;
+
+ if (lcdb->ttw_enable) {
+ rc = qpnp_lcdb_ttw_enter(lcdb);
+ if (rc < 0) {
+ pr_err("Failed to enable TTW mode rc=%d\n", rc);
+ return rc;
+ }
+ lcdb->lcdb_enabled = false;
+
+ return 0;
+ }
+
+ val = 0;
+ rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_ENABLE_CTL1_REG,
+ &val, 1);
+ if (rc < 0)
+ pr_err("Failed to disable lcdb rc= %d\n", rc);
+ else
+ lcdb->lcdb_enabled = false;
+
+ return rc;
+}
+
+#define MIN_BST_VOLTAGE_MV 4700
+#define MAX_BST_VOLTAGE_MV 6250
+#define MIN_VOLTAGE_MV 4000
+#define MAX_VOLTAGE_MV 6000
+#define VOLTAGE_MIN_STEP_100_MV 4000
+#define VOLTAGE_MIN_STEP_50_MV 4950
+#define VOLTAGE_STEP_100_MV 100
+#define VOLTAGE_STEP_50_MV 50
+#define VOLTAGE_STEP_50MV_OFFSET 0xA
+static int qpnp_lcdb_set_bst_voltage(struct qpnp_lcdb *lcdb,
+ int voltage_mv)
+{
+ int rc = 0;
+ u8 val = 0;
+
+ if (voltage_mv < MIN_BST_VOLTAGE_MV)
+ voltage_mv = MIN_BST_VOLTAGE_MV;
+ else if (voltage_mv > MAX_BST_VOLTAGE_MV)
+ voltage_mv = MAX_BST_VOLTAGE_MV;
+
+ val = DIV_ROUND_UP(voltage_mv - MIN_BST_VOLTAGE_MV,
+ VOLTAGE_STEP_50_MV);
+
+ rc = qpnp_lcdb_masked_write(lcdb, lcdb->base +
+ LCDB_BST_OUTPUT_VOLTAGE_REG,
+ SET_OUTPUT_VOLTAGE_MASK, val);
+ if (rc < 0)
+ pr_err("Failed to set boost voltage %d mv rc=%d\n",
+ voltage_mv, rc);
+ else
+ pr_debug("Boost voltage set = %d mv (0x%02x = 0x%02x)\n",
+ voltage_mv, LCDB_BST_OUTPUT_VOLTAGE_REG, val);
+
+ return rc;
+}
+
+static int qpnp_lcdb_get_bst_voltage(struct qpnp_lcdb *lcdb,
+ int *voltage_mv)
+{
+ int rc;
+ u8 val = 0;
+
+ rc = qpnp_lcdb_read(lcdb, lcdb->base + LCDB_BST_OUTPUT_VOLTAGE_REG,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to reat BST voltage rc=%d\n", rc);
+ return rc;
+ }
+
+ val &= SET_OUTPUT_VOLTAGE_MASK;
+ *voltage_mv = (val * VOLTAGE_STEP_50_MV) + MIN_BST_VOLTAGE_MV;
+
+ return 0;
+}
+
+static int qpnp_lcdb_set_voltage(struct qpnp_lcdb *lcdb,
+ int voltage_mv, u8 type)
+{
+ int rc = 0;
+ u16 offset = LCDB_LDO_OUTPUT_VOLTAGE_REG;
+ u8 val = 0;
+
+ if (type == BST)
+ return qpnp_lcdb_set_bst_voltage(lcdb, voltage_mv);
+
+ if (type == NCP)
+ offset = LCDB_NCP_OUTPUT_VOLTAGE_REG;
+
+ if (!is_between(voltage_mv, MIN_VOLTAGE_MV, MAX_VOLTAGE_MV)) {
+ pr_err("Invalid voltage %dmv (min=%d max=%d)\n",
+ voltage_mv, MIN_VOLTAGE_MV, MAX_VOLTAGE_MV);
+ return -EINVAL;
+ }
+
+ /* Change the BST voltage to LDO + 100mV */
+ if (type == LDO) {
+ rc = qpnp_lcdb_set_bst_voltage(lcdb, voltage_mv + 100);
+ if (rc < 0) {
+ pr_err("Failed to set boost voltage rc=%d\n", rc);
+ return rc;
+ }
+ }
+
+ /* Below logic is only valid for LDO and NCP type */
+ if (voltage_mv < VOLTAGE_MIN_STEP_50_MV) {
+ val = DIV_ROUND_UP(voltage_mv - VOLTAGE_MIN_STEP_100_MV,
+ VOLTAGE_STEP_100_MV);
+ } else {
+ val = DIV_ROUND_UP(voltage_mv - VOLTAGE_MIN_STEP_50_MV,
+ VOLTAGE_STEP_50_MV);
+ val += VOLTAGE_STEP_50MV_OFFSET;
+ }
+
+ rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + offset,
+ SET_OUTPUT_VOLTAGE_MASK, val);
+ if (rc < 0)
+ pr_err("Failed to set output voltage %d mv for %s rc=%d\n",
+ voltage_mv, (type == LDO) ? "LDO" : "NCP", rc);
+ else
+ pr_debug("%s voltage set = %d mv (0x%02x = 0x%02x)\n",
+ (type == LDO) ? "LDO" : "NCP", voltage_mv, offset, val);
+
+ return rc;
+}
+
+static int qpnp_lcdb_get_voltage(struct qpnp_lcdb *lcdb,
+ u32 *voltage_mv, u8 type)
+{
+ int rc = 0;
+ u16 offset = LCDB_LDO_OUTPUT_VOLTAGE_REG;
+ u8 val = 0;
+
+ if (type == BST)
+ return qpnp_lcdb_get_bst_voltage(lcdb, voltage_mv);
+
+ if (type == NCP)
+ offset = LCDB_NCP_OUTPUT_VOLTAGE_REG;
+
+ rc = qpnp_lcdb_read(lcdb, lcdb->base + offset, &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to read %s volatge rc=%d\n",
+ (type == LDO) ? "LDO" : "NCP", rc);
+ return rc;
+ }
+
+ if (val < VOLTAGE_STEP_50MV_OFFSET) {
+ *voltage_mv = VOLTAGE_MIN_STEP_100_MV +
+ (val * VOLTAGE_STEP_100_MV);
+ } else {
+ *voltage_mv = VOLTAGE_MIN_STEP_50_MV +
+ ((val - VOLTAGE_STEP_50MV_OFFSET) * VOLTAGE_STEP_50_MV);
+ }
+
+ if (!rc)
+ pr_debug("%s voltage read-back = %d mv (0x%02x = 0x%02x)\n",
+ (type == LDO) ? "LDO" : "NCP",
+ *voltage_mv, offset, val);
+
+ return rc;
+}
+
+static int qpnp_lcdb_set_soft_start(struct qpnp_lcdb *lcdb,
+ u32 ss_us, u8 type)
+{
+ int rc = 0, i = 0;
+ u16 offset = LCDB_LDO_SOFT_START_CTL_REG;
+ u8 val = 0;
+
+ if (type == NCP)
+ offset = LCDB_NCP_SOFT_START_CTL_REG;
+
+ if (!is_between(ss_us, MIN_SOFT_START_US, MAX_SOFT_START_US)) {
+ pr_err("Invalid soft_start_us %d (min=%d max=%d)\n",
+ ss_us, MIN_SOFT_START_US, MAX_SOFT_START_US);
+ return -EINVAL;
+ }
+
+ i = 0;
+ while (ss_us > soft_start_us[i])
+ i++;
+ val = ((i == 0) ? 0 : i - 1) & SOFT_START_MASK;
+
+ rc = qpnp_lcdb_masked_write(lcdb,
+ lcdb->base + offset, SOFT_START_MASK, val);
+ if (rc < 0)
+ pr_err("Failed to write %s soft-start time %d rc=%d",
+ (type == LDO) ? "LDO" : "NCP", soft_start_us[i], rc);
+
+ return rc;
+}
+
+static int qpnp_lcdb_ldo_regulator_enable(struct regulator_dev *rdev)
+{
+ int rc = 0;
+ struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev);
+
+ mutex_lock(&lcdb->lcdb_mutex);
+ rc = qpnp_lcdb_enable(lcdb);
+ if (rc < 0)
+ pr_err("Failed to enable lcdb rc=%d\n", rc);
+ mutex_unlock(&lcdb->lcdb_mutex);
+
+ return rc;
+}
+
+static int qpnp_lcdb_ldo_regulator_disable(struct regulator_dev *rdev)
+{
+ int rc = 0;
+ struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev);
+
+ mutex_lock(&lcdb->lcdb_mutex);
+ rc = qpnp_lcdb_disable(lcdb);
+ if (rc < 0)
+ pr_err("Failed to disable lcdb rc=%d\n", rc);
+ mutex_unlock(&lcdb->lcdb_mutex);
+
+ return rc;
+}
+
+static int qpnp_lcdb_ldo_regulator_is_enabled(struct regulator_dev *rdev)
+{
+ struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev);
+
+ return lcdb->lcdb_enabled;
+}
+
+static int qpnp_lcdb_ldo_regulator_set_voltage(struct regulator_dev *rdev,
+ int min_uV, int max_uV, unsigned int *selector)
+{
+ int rc = 0;
+ struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev);
+
+ rc = qpnp_lcdb_set_voltage(lcdb, min_uV / 1000, LDO);
+ if (rc < 0)
+ pr_err("Failed to set LDO voltage rc=%c\n", rc);
+
+ return rc;
+}
+
+static int qpnp_lcdb_ldo_regulator_get_voltage(struct regulator_dev *rdev)
+{
+ int rc = 0;
+ u32 voltage_mv = 0;
+ struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev);
+
+ rc = qpnp_lcdb_get_voltage(lcdb, &voltage_mv, LDO);
+ if (rc < 0) {
+ pr_err("Failed to get ldo voltage rc=%d\n", rc);
+ return rc;
+ }
+
+ return voltage_mv * 1000;
+}
+
+static struct regulator_ops qpnp_lcdb_ldo_ops = {
+ .enable = qpnp_lcdb_ldo_regulator_enable,
+ .disable = qpnp_lcdb_ldo_regulator_disable,
+ .is_enabled = qpnp_lcdb_ldo_regulator_is_enabled,
+ .set_voltage = qpnp_lcdb_ldo_regulator_set_voltage,
+ .get_voltage = qpnp_lcdb_ldo_regulator_get_voltage,
+};
+
+static int qpnp_lcdb_ncp_regulator_enable(struct regulator_dev *rdev)
+{
+ int rc = 0;
+ struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev);
+
+ mutex_lock(&lcdb->lcdb_mutex);
+ rc = qpnp_lcdb_enable(lcdb);
+ if (rc < 0)
+ pr_err("Failed to enable lcdb rc=%d\n", rc);
+ mutex_unlock(&lcdb->lcdb_mutex);
+
+ return rc;
+}
+
+static int qpnp_lcdb_ncp_regulator_disable(struct regulator_dev *rdev)
+{
+ int rc = 0;
+ struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev);
+
+ mutex_lock(&lcdb->lcdb_mutex);
+ rc = qpnp_lcdb_disable(lcdb);
+ if (rc < 0)
+ pr_err("Failed to disable lcdb rc=%d\n", rc);
+ mutex_unlock(&lcdb->lcdb_mutex);
+
+ return rc;
+}
+
+static int qpnp_lcdb_ncp_regulator_is_enabled(struct regulator_dev *rdev)
+{
+ struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev);
+
+ return lcdb->lcdb_enabled;
+}
+
+static int qpnp_lcdb_ncp_regulator_set_voltage(struct regulator_dev *rdev,
+ int min_uV, int max_uV, unsigned int *selector)
+{
+ int rc = 0;
+ struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev);
+
+ rc = qpnp_lcdb_set_voltage(lcdb, min_uV / 1000, NCP);
+ if (rc < 0)
+ pr_err("Failed to set LDO voltage rc=%c\n", rc);
+
+ return rc;
+}
+
+static int qpnp_lcdb_ncp_regulator_get_voltage(struct regulator_dev *rdev)
+{
+ int rc;
+ u32 voltage_mv = 0;
+ struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev);
+
+ rc = qpnp_lcdb_get_voltage(lcdb, &voltage_mv, NCP);
+ if (rc < 0) {
+ pr_err("Failed to get ncp voltage rc=%d\n", rc);
+ return rc;
+ }
+
+ return voltage_mv * 1000;
+}
+
+static struct regulator_ops qpnp_lcdb_ncp_ops = {
+ .enable = qpnp_lcdb_ncp_regulator_enable,
+ .disable = qpnp_lcdb_ncp_regulator_disable,
+ .is_enabled = qpnp_lcdb_ncp_regulator_is_enabled,
+ .set_voltage = qpnp_lcdb_ncp_regulator_set_voltage,
+ .get_voltage = qpnp_lcdb_ncp_regulator_get_voltage,
+};
+
+static int qpnp_lcdb_regulator_register(struct qpnp_lcdb *lcdb, u8 type)
+{
+ int rc = 0;
+ struct regulator_init_data *init_data;
+ struct regulator_config cfg = {};
+ struct regulator_desc *rdesc;
+ struct regulator_dev *rdev;
+ struct device_node *node;
+
+ if (type == LDO) {
+ node = lcdb->ldo.node;
+ rdesc = &lcdb->ldo.rdesc;
+ rdesc->ops = &qpnp_lcdb_ldo_ops;
+ rdev = lcdb->ldo.rdev;
+ } else if (type == NCP) {
+ node = lcdb->ncp.node;
+ rdesc = &lcdb->ncp.rdesc;
+ rdesc->ops = &qpnp_lcdb_ncp_ops;
+ rdev = lcdb->ncp.rdev;
+ } else {
+ pr_err("Invalid regulator type %d\n", type);
+ return -EINVAL;
+ }
+
+ init_data = of_get_regulator_init_data(lcdb->dev, node, rdesc);
+ if (!init_data) {
+ pr_err("Failed to get regulator_init_data for %s\n",
+ (type == LDO) ? "LDO" : "NCP");
+ return -ENOMEM;
+ }
+
+ if (init_data->constraints.name) {
+ rdesc->owner = THIS_MODULE;
+ rdesc->type = REGULATOR_VOLTAGE;
+ rdesc->name = init_data->constraints.name;
+
+ cfg.dev = lcdb->dev;
+ cfg.init_data = init_data;
+ cfg.driver_data = lcdb;
+ cfg.of_node = node;
+
+ if (of_get_property(lcdb->dev->of_node, "parent-supply", NULL))
+ init_data->supply_regulator = "parent";
+
+ init_data->constraints.valid_ops_mask
+ |= REGULATOR_CHANGE_VOLTAGE
+ | REGULATOR_CHANGE_STATUS;
+
+ rdev = devm_regulator_register(lcdb->dev, rdesc, &cfg);
+ if (IS_ERR(rdev)) {
+ rc = PTR_ERR(rdev);
+ rdev = NULL;
+ pr_err("Failed to register lcdb_%s regulator rc = %d\n",
+ (type == LDO) ? "LDO" : "NCP", rc);
+ return rc;
+ }
+ } else {
+ pr_err("%s_regulator name missing\n",
+ (type == LDO) ? "LDO" : "NCP");
+ return -EINVAL;
+ }
+
+ return rc;
+}
+
+static int qpnp_lcdb_parse_ttw(struct qpnp_lcdb *lcdb)
+{
+ int rc = 0;
+ u32 temp;
+ u8 val = 0;
+ struct device_node *node = lcdb->dev->of_node;
+
+ if (of_property_read_bool(node, "qcom,ttw-mode-sw")) {
+ lcdb->ttw_mode_sw = true;
+ rc = of_property_read_u32(node, "qcom,attw-toff-ms", &temp);
+ if (!rc) {
+ if (!is_between(temp, ATTW_MIN_MS, ATTW_MAX_MS)) {
+ pr_err("Invalid TOFF val %d (min=%d max=%d)\n",
+ temp, ATTW_MIN_MS, ATTW_MAX_MS);
+ return -EINVAL;
+ }
+ val = ilog2(temp / 4) << ATTW_TOFF_TIME_SHIFT;
+ } else {
+ pr_err("qcom,attw-toff-ms not specified for TTW SW mode\n");
+ return rc;
+ }
+
+ rc = of_property_read_u32(node, "qcom,attw-ton-ms", &temp);
+ if (!rc) {
+ if (!is_between(temp, ATTW_MIN_MS, ATTW_MAX_MS)) {
+ pr_err("Invalid TON value %d (min=%d max=%d)\n",
+ temp, ATTW_MIN_MS, ATTW_MAX_MS);
+ return -EINVAL;
+ }
+ val |= ilog2(temp / 4);
+ } else {
+ pr_err("qcom,attw-ton-ms not specified for TTW SW mode\n");
+ return rc;
+ }
+ rc = qpnp_lcdb_masked_write(lcdb, lcdb->base +
+ LCDB_AUTO_TOUCH_WAKE_CTL_REG,
+ ATTW_TON_TIME_MASK | ATTW_TOFF_TIME_MASK, val);
+ if (rc < 0) {
+ pr_err("Failed to write ATTW ON/OFF rc=%d\n", rc);
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+static int qpnp_lcdb_ldo_dt_init(struct qpnp_lcdb *lcdb)
+{
+ int rc = 0;
+ struct device_node *node = lcdb->ldo.node;
+
+ /* LDO output voltage */
+ lcdb->ldo.voltage_mv = -EINVAL;
+ rc = of_property_read_u32(node, "qcom,ldo-voltage-mv",
+ &lcdb->ldo.voltage_mv);
+ if (!rc && !is_between(lcdb->ldo.voltage_mv, MIN_VOLTAGE_MV,
+ MAX_VOLTAGE_MV)) {
+ pr_err("Invalid LDO voltage %dmv (min=%d max=%d)\n",
+ lcdb->ldo.voltage_mv, MIN_VOLTAGE_MV, MAX_VOLTAGE_MV);
+ return -EINVAL;
+ }
+
+ /* LDO PD configuration */
+ lcdb->ldo.pd = -EINVAL;
+ of_property_read_u32(node, "qcom,ldo-pd", &lcdb->ldo.pd);
+
+ lcdb->ldo.pd_strength = -EINVAL;
+ of_property_read_u32(node, "qcom,ldo-pd-strength",
+ &lcdb->ldo.pd_strength);
+
+ /* LDO ILIM configuration */
+ lcdb->ldo.ilim_ma = -EINVAL;
+ rc = of_property_read_u32(node, "qcom,ldo-ilim-ma", &lcdb->ldo.ilim_ma);
+ if (!rc && !is_between(lcdb->ldo.ilim_ma, MIN_LDO_ILIM_MA,
+ MAX_LDO_ILIM_MA)) {
+ pr_err("Invalid ilim_ma %d (min=%d, max=%d)\n",
+ lcdb->ldo.ilim_ma, MIN_LDO_ILIM_MA,
+ MAX_LDO_ILIM_MA);
+ return -EINVAL;
+ }
+
+ /* LDO soft-start (SS) configuration */
+ lcdb->ldo.soft_start_us = -EINVAL;
+ of_property_read_u32(node, "qcom,ldo-soft-start-us",
+ &lcdb->ldo.soft_start_us);
+
+ return 0;
+}
+
+static int qpnp_lcdb_ncp_dt_init(struct qpnp_lcdb *lcdb)
+{
+ int rc = 0;
+ struct device_node *node = lcdb->ncp.node;
+
+ /* NCP output voltage */
+ lcdb->ncp.voltage_mv = -EINVAL;
+ rc = of_property_read_u32(node, "qcom,ncp-voltage-mv",
+ &lcdb->ncp.voltage_mv);
+ if (!rc && !is_between(lcdb->ncp.voltage_mv, MIN_VOLTAGE_MV,
+ MAX_VOLTAGE_MV)) {
+ pr_err("Invalid NCP voltage %dmv (min=%d max=%d)\n",
+ lcdb->ldo.voltage_mv, MIN_VOLTAGE_MV, MAX_VOLTAGE_MV);
+ return -EINVAL;
+ }
+
+ /* NCP PD configuration */
+ lcdb->ncp.pd = -EINVAL;
+ of_property_read_u32(node, "qcom,ncp-pd", &lcdb->ncp.pd);
+
+ lcdb->ncp.pd_strength = -EINVAL;
+ of_property_read_u32(node, "qcom,ncp-pd-strength",
+ &lcdb->ncp.pd_strength);
+
+ /* NCP ILIM configuration */
+ lcdb->ncp.ilim_ma = -EINVAL;
+ rc = of_property_read_u32(node, "qcom,ncp-ilim-ma", &lcdb->ncp.ilim_ma);
+ if (!rc && !is_between(lcdb->ncp.ilim_ma, MIN_NCP_ILIM_MA,
+ MAX_NCP_ILIM_MA)) {
+ pr_err("Invalid ilim_ma %d (min=%d, max=%d)\n",
+ lcdb->ncp.ilim_ma, MIN_NCP_ILIM_MA, MAX_NCP_ILIM_MA);
+ return -EINVAL;
+ }
+
+ /* NCP soft-start (SS) configuration */
+ lcdb->ncp.soft_start_us = -EINVAL;
+ of_property_read_u32(node, "qcom,ncp-soft-start-us",
+ &lcdb->ncp.soft_start_us);
+
+ return 0;
+}
+
+static int qpnp_lcdb_bst_dt_init(struct qpnp_lcdb *lcdb)
+{
+ int rc = 0;
+ struct device_node *node = lcdb->bst.node;
+
+ /* Boost PD configuration */
+ lcdb->bst.pd = -EINVAL;
+ of_property_read_u32(node, "qcom,bst-pd", &lcdb->bst.pd);
+
+ lcdb->bst.pd_strength = -EINVAL;
+ of_property_read_u32(node, "qcom,bst-pd-strength",
+ &lcdb->bst.pd_strength);
+
+ /* Boost ILIM */
+ lcdb->bst.ilim_ma = -EINVAL;
+ rc = of_property_read_u32(node, "qcom,bst-ilim-ma", &lcdb->bst.ilim_ma);
+ if (!rc && !is_between(lcdb->bst.ilim_ma, MIN_BST_ILIM_MA,
+ MAX_BST_ILIM_MA)) {
+ pr_err("Invalid ilim_ma %d (min=%d, max=%d)\n",
+ lcdb->bst.ilim_ma, MIN_BST_ILIM_MA, MAX_BST_ILIM_MA);
+ return -EINVAL;
+ }
+
+ /* Boost PS configuration */
+ lcdb->bst.ps = -EINVAL;
+ of_property_read_u32(node, "qcom,bst-ps", &lcdb->bst.ps);
+
+ lcdb->bst.ps_threshold = -EINVAL;
+ rc = of_property_read_u32(node, "qcom,bst-ps-threshold-ma",
+ &lcdb->bst.ps_threshold);
+ if (!rc && !is_between(lcdb->bst.ps_threshold,
+ MIN_BST_PS_MA, MAX_BST_PS_MA)) {
+ pr_err("Invalid bst ps_threshold %d (min=%d, max=%d)\n",
+ lcdb->bst.ps_threshold, MIN_BST_PS_MA, MAX_BST_PS_MA);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int qpnp_lcdb_init_ldo(struct qpnp_lcdb *lcdb)
+{
+ int rc = 0, ilim_ma;
+ u8 val = 0;
+
+ /* configure parameters only if LCDB is disabled */
+ if (!is_lcdb_enabled(lcdb)) {
+ if (lcdb->ldo.voltage_mv != -EINVAL) {
+ rc = qpnp_lcdb_set_voltage(lcdb,
+ lcdb->ldo.voltage_mv, LDO);
+ if (rc < 0) {
+ pr_err("Failed to set voltage rc=%d\n", rc);
+ return rc;
+ }
+ }
+
+ if (lcdb->ldo.pd != -EINVAL) {
+ rc = qpnp_lcdb_masked_write(lcdb, lcdb->base +
+ LCDB_LDO_PD_CTL_REG, LDO_DIS_PULLDOWN_BIT,
+ lcdb->ldo.pd ? 0 : LDO_DIS_PULLDOWN_BIT);
+ if (rc < 0) {
+ pr_err("Failed to configure LDO PD rc=%d\n",
+ rc);
+ return rc;
+ }
+ }
+
+ if (lcdb->ldo.pd_strength != -EINVAL) {
+ rc = qpnp_lcdb_masked_write(lcdb, lcdb->base +
+ LCDB_LDO_PD_CTL_REG, LDO_PD_STRENGTH_BIT,
+ lcdb->ldo.pd_strength ?
+ LDO_PD_STRENGTH_BIT : 0);
+ if (rc < 0) {
+ pr_err("Failed to configure LDO PD strength %s rc=%d",
+ lcdb->ldo.pd_strength ?
+ "(strong)" : "(weak)", rc);
+ return rc;
+ }
+ }
+
+ if (lcdb->ldo.ilim_ma != -EINVAL) {
+ ilim_ma = lcdb->ldo.ilim_ma - MIN_LDO_ILIM_MA;
+ ilim_ma /= LDO_ILIM_STEP_MA;
+ val = (ilim_ma & SET_LDO_ILIM_MASK) | EN_LDO_ILIM_BIT;
+ rc = qpnp_lcdb_masked_write(lcdb, lcdb->base +
+ LCDB_LDO_ILIM_CTL1_REG,
+ SET_LDO_ILIM_MASK | EN_LDO_ILIM_BIT,
+ val);
+ if (rc < 0) {
+ pr_err("Failed to configure LDO ilim_ma (CTL1=%d) rc=%d",
+ val, rc);
+ return rc;
+ }
+
+ val = ilim_ma & SET_LDO_ILIM_MASK;
+ rc = qpnp_lcdb_masked_write(lcdb,
+ lcdb->base + LCDB_LDO_ILIM_CTL2_REG,
+ SET_LDO_ILIM_MASK, val);
+ if (rc < 0) {
+ pr_err("Failed to configure LDO ilim_ma (CTL2=%d) rc=%d",
+ val, rc);
+ return rc;
+ }
+ }
+
+ if (lcdb->ldo.soft_start_us != -EINVAL) {
+ rc = qpnp_lcdb_set_soft_start(lcdb,
+ lcdb->ldo.soft_start_us, LDO);
+ if (rc < 0) {
+ pr_err("Failed to set LDO soft_start rc=%d\n",
+ rc);
+ return rc;
+ }
+ }
+ }
+
+ rc = qpnp_lcdb_get_voltage(lcdb, &lcdb->ldo.voltage_mv, LDO);
+ if (rc < 0) {
+ pr_err("Failed to get LDO volatge rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = qpnp_lcdb_read(lcdb, lcdb->base +
+ LCDB_LDO_VREG_OK_CTL_REG, &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to read ldo_vreg_ok rc=%d\n", rc);
+ return rc;
+ }
+ lcdb->ldo.vreg_ok_dbc_us = dbc_us[val & VREG_OK_DEB_MASK];
+
+ rc = qpnp_lcdb_read(lcdb, lcdb->base +
+ LCDB_LDO_SOFT_START_CTL_REG, &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to read ldo_soft_start_ctl rc=%d\n", rc);
+ return rc;
+ }
+ lcdb->ldo.soft_start_us = soft_start_us[val & SOFT_START_MASK];
+
+ rc = qpnp_lcdb_regulator_register(lcdb, LDO);
+ if (rc < 0)
+ pr_err("Failed to register ldo rc=%d\n", rc);
+
+ return rc;
+}
+
+static int qpnp_lcdb_init_ncp(struct qpnp_lcdb *lcdb)
+{
+ int rc = 0, i = 0;
+ u8 val = 0;
+
+ /* configure parameters only if LCDB is disabled */
+ if (!is_lcdb_enabled(lcdb)) {
+ if (lcdb->ncp.voltage_mv != -EINVAL) {
+ rc = qpnp_lcdb_set_voltage(lcdb,
+ lcdb->ncp.voltage_mv, NCP);
+ if (rc < 0) {
+ pr_err("Failed to set voltage rc=%d\n", rc);
+ return rc;
+ }
+ }
+
+ if (lcdb->ncp.pd != -EINVAL) {
+ rc = qpnp_lcdb_masked_write(lcdb, lcdb->base +
+ LCDB_NCP_PD_CTL_REG, NCP_DIS_PULLDOWN_BIT,
+ lcdb->ncp.pd ? 0 : NCP_DIS_PULLDOWN_BIT);
+ if (rc < 0) {
+ pr_err("Failed to configure NCP PD rc=%d\n",
+ rc);
+ return rc;
+ }
+ }
+
+ if (lcdb->ncp.pd_strength != -EINVAL) {
+ rc = qpnp_lcdb_masked_write(lcdb, lcdb->base +
+ LCDB_NCP_PD_CTL_REG, NCP_PD_STRENGTH_BIT,
+ lcdb->ncp.pd_strength ?
+ NCP_PD_STRENGTH_BIT : 0);
+ if (rc < 0) {
+ pr_err("Failed to configure NCP PD strength %s rc=%d",
+ lcdb->ncp.pd_strength ?
+ "(strong)" : "(weak)", rc);
+ return rc;
+ }
+ }
+
+ if (lcdb->ncp.ilim_ma != -EINVAL) {
+ while (lcdb->ncp.ilim_ma > ncp_ilim_ma[i])
+ i++;
+ val = (i == 0) ? 0 : i - 1;
+ val = (lcdb->ncp.ilim_ma & SET_NCP_ILIM_MASK) |
+ EN_NCP_ILIM_BIT;
+ rc = qpnp_lcdb_masked_write(lcdb, lcdb->base +
+ LCDB_NCP_ILIM_CTL1_REG,
+ SET_NCP_ILIM_MASK | EN_NCP_ILIM_BIT, val);
+ if (rc < 0) {
+ pr_err("Failed to configure NCP ilim_ma (CTL1=%d) rc=%d",
+ val, rc);
+ return rc;
+ }
+ val = lcdb->ncp.ilim_ma & SET_NCP_ILIM_MASK;
+ rc = qpnp_lcdb_masked_write(lcdb,
+ lcdb->base + LCDB_NCP_ILIM_CTL2_REG,
+ SET_NCP_ILIM_MASK, val);
+ if (rc < 0) {
+ pr_err("Failed to configure NCP ilim_ma (CTL2=%d) rc=%d",
+ val, rc);
+ return rc;
+ }
+ }
+
+ if (lcdb->ncp.soft_start_us != -EINVAL) {
+ rc = qpnp_lcdb_set_soft_start(lcdb,
+ lcdb->ncp.soft_start_us, NCP);
+ if (rc < 0) {
+ pr_err("Failed to set NCP soft_start rc=%d\n",
+ rc);
+ return rc;
+ }
+ }
+ }
+
+ rc = qpnp_lcdb_get_voltage(lcdb, &lcdb->ncp.voltage_mv, NCP);
+ if (rc < 0) {
+ pr_err("Failed to get NCP volatge rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = qpnp_lcdb_read(lcdb, lcdb->base +
+ LCDB_NCP_VREG_OK_CTL_REG, &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to read ncp_vreg_ok rc=%d\n", rc);
+ return rc;
+ }
+ lcdb->ncp.vreg_ok_dbc_us = dbc_us[val & VREG_OK_DEB_MASK];
+
+ rc = qpnp_lcdb_read(lcdb, lcdb->base +
+ LCDB_NCP_SOFT_START_CTL_REG, &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to read ncp_soft_start_ctl rc=%d\n", rc);
+ return rc;
+ }
+ lcdb->ncp.soft_start_us = soft_start_us[val & SOFT_START_MASK];
+
+ rc = qpnp_lcdb_regulator_register(lcdb, NCP);
+ if (rc < 0)
+ pr_err("Failed to register NCP rc=%d\n", rc);
+
+ return rc;
+}
+
+static int qpnp_lcdb_init_bst(struct qpnp_lcdb *lcdb)
+{
+ int rc = 0;
+ u8 val = 0;
+
+ /* configure parameters only if LCDB is disabled */
+ if (!is_lcdb_enabled(lcdb)) {
+ if (lcdb->bst.pd != -EINVAL) {
+ rc = qpnp_lcdb_masked_write(lcdb, lcdb->base +
+ LCDB_BST_PD_CTL_REG, BOOST_DIS_PULLDOWN_BIT,
+ lcdb->bst.pd ? 0 : BOOST_DIS_PULLDOWN_BIT);
+ if (rc < 0) {
+ pr_err("Failed to configure BST PD rc=%d\n",
+ rc);
+ return rc;
+ }
+ }
+
+ if (lcdb->bst.pd_strength != -EINVAL) {
+ rc = qpnp_lcdb_masked_write(lcdb, lcdb->base +
+ LCDB_NCP_PD_CTL_REG, BOOST_PD_STRENGTH_BIT,
+ lcdb->bst.pd_strength ?
+ BOOST_PD_STRENGTH_BIT : 0);
+ if (rc < 0) {
+ pr_err("Failed to configure NCP PD strength %s rc=%d",
+ lcdb->bst.pd_strength ?
+ "(strong)" : "(weak)", rc);
+ return rc;
+ }
+ }
+
+ if (lcdb->bst.ilim_ma != -EINVAL) {
+ val = (lcdb->bst.ilim_ma / MIN_BST_ILIM_MA) - 1;
+ val = (lcdb->bst.ilim_ma & SET_BST_ILIM_MASK) |
+ EN_BST_ILIM_BIT;
+ rc = qpnp_lcdb_masked_write(lcdb, lcdb->base +
+ LCDB_BST_ILIM_CTL_REG,
+ SET_BST_ILIM_MASK | EN_BST_ILIM_BIT, val);
+ if (rc < 0) {
+ pr_err("Failed to configure BST ilim_ma rc=%d",
+ rc);
+ return rc;
+ }
+ }
+
+ if (lcdb->bst.ps != -EINVAL) {
+ rc = qpnp_lcdb_masked_write(lcdb, lcdb->base +
+ LCDB_PS_CTL_REG, EN_PS_BIT,
+ &lcdb->bst.ps ? EN_PS_BIT : 0);
+ if (rc < 0) {
+ pr_err("Failed to disable BST PS rc=%d", rc);
+ return rc;
+ }
+ }
+
+ if (lcdb->bst.ps_threshold != -EINVAL) {
+ val = (lcdb->bst.ps_threshold - MIN_BST_PS_MA) / 10;
+ val = (lcdb->bst.ps_threshold & PS_THRESHOLD_MASK) |
+ EN_PS_BIT;
+ rc = qpnp_lcdb_masked_write(lcdb, lcdb->base +
+ LCDB_PS_CTL_REG,
+ PS_THRESHOLD_MASK | EN_PS_BIT,
+ val);
+ if (rc < 0) {
+ pr_err("Failed to configure BST PS threshold rc=%d",
+ rc);
+ return rc;
+ }
+ }
+ }
+
+ rc = qpnp_lcdb_get_voltage(lcdb, &lcdb->bst.voltage_mv, BST);
+ if (rc < 0) {
+ pr_err("Failed to get BST volatge rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = qpnp_lcdb_read(lcdb, lcdb->base +
+ LCDB_BST_VREG_OK_CTL_REG, &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to read bst_vreg_ok rc=%d\n", rc);
+ return rc;
+ }
+ lcdb->bst.vreg_ok_dbc_us = dbc_us[val & VREG_OK_DEB_MASK];
+
+ rc = qpnp_lcdb_read(lcdb, lcdb->base +
+ LCDB_SOFT_START_CTL_REG, &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to read ncp_soft_start_ctl rc=%d\n", rc);
+ return rc;
+ }
+ lcdb->bst.soft_start_us = (val & SOFT_START_MASK) * 200 + 200;
+
+ return 0;
+}
+
+static int qpnp_lcdb_hw_init(struct qpnp_lcdb *lcdb)
+{
+ int rc = 0;
+ u8 val = 0;
+
+ rc = qpnp_lcdb_init_bst(lcdb);
+ if (rc < 0) {
+ pr_err("Failed to initialize BOOST rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = qpnp_lcdb_init_ldo(lcdb);
+ if (rc < 0) {
+ pr_err("Failed to initialize LDO rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = qpnp_lcdb_init_ncp(lcdb);
+ if (rc < 0) {
+ pr_err("Failed to initialize NCP rc=%d\n", rc);
+ return rc;
+ }
+
+ if (!is_lcdb_enabled(lcdb)) {
+ rc = qpnp_lcdb_read(lcdb, lcdb->base +
+ LCDB_MODULE_RDY_REG, &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to read MODULE_RDY rc=%d\n", rc);
+ return rc;
+ }
+ if (!(val & MODULE_RDY_BIT)) {
+ rc = qpnp_lcdb_masked_write(lcdb, lcdb->base +
+ LCDB_MODULE_RDY_REG, MODULE_RDY_BIT,
+ MODULE_RDY_BIT);
+ if (rc < 0) {
+ pr_err("Failed to set MODULE RDY rc=%d\n", rc);
+ return rc;
+ }
+ }
+ } else {
+ /* module already enabled */
+ lcdb->lcdb_enabled = true;
+ }
+
+ return 0;
+}
+
+static int qpnp_lcdb_parse_dt(struct qpnp_lcdb *lcdb)
+{
+ int rc = 0;
+ const char *label;
+ struct device_node *temp, *node = lcdb->dev->of_node;
+
+ for_each_available_child_of_node(node, temp) {
+ rc = of_property_read_string(temp, "label", &label);
+ if (rc < 0) {
+ pr_err("Failed to read label rc=%d\n", rc);
+ return rc;
+ }
+
+ if (!strcmp(label, "ldo")) {
+ lcdb->ldo.node = temp;
+ rc = qpnp_lcdb_ldo_dt_init(lcdb);
+ } else if (!strcmp(label, "ncp")) {
+ lcdb->ncp.node = temp;
+ rc = qpnp_lcdb_ncp_dt_init(lcdb);
+ } else if (!strcmp(label, "bst")) {
+ lcdb->bst.node = temp;
+ rc = qpnp_lcdb_bst_dt_init(lcdb);
+ } else {
+ pr_err("Failed to identify label %s\n", label);
+ return -EINVAL;
+ }
+ if (rc < 0) {
+ pr_err("Failed to register %s module\n", label);
+ return rc;
+ }
+ }
+
+ if (of_property_read_bool(node, "qcom,ttw-enable")) {
+ rc = qpnp_lcdb_parse_ttw(lcdb);
+ if (rc < 0) {
+ pr_err("Failed to parse ttw-params rc=%d\n", rc);
+ return rc;
+ }
+ lcdb->ttw_enable = true;
+ }
+
+ return rc;
+}
+
+static int qpnp_lcdb_regulator_probe(struct platform_device *pdev)
+{
+ int rc;
+ struct device_node *node;
+ struct qpnp_lcdb *lcdb;
+
+ node = pdev->dev.of_node;
+ if (!node) {
+ pr_err("No nodes defined\n");
+ return -ENODEV;
+ }
+
+ lcdb = devm_kzalloc(&pdev->dev, sizeof(*lcdb), GFP_KERNEL);
+ if (!lcdb)
+ return -ENOMEM;
+
+ rc = of_property_read_u32(node, "reg", &lcdb->base);
+ if (rc < 0) {
+ pr_err("Failed to find reg node rc=%d\n", rc);
+ return rc;
+ }
+
+ lcdb->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (!lcdb->regmap) {
+ pr_err("Failed to get the regmap handle rc=%d\n", rc);
+ return -EINVAL;
+ }
+
+ lcdb->dev = &pdev->dev;
+ lcdb->pdev = pdev;
+ mutex_init(&lcdb->lcdb_mutex);
+ mutex_init(&lcdb->read_write_mutex);
+
+ rc = qpnp_lcdb_parse_dt(lcdb);
+ if (rc < 0) {
+ pr_err("Failed to parse dt rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = qpnp_lcdb_hw_init(lcdb);
+ if (rc < 0)
+ pr_err("Failed to initialize LCDB module rc=%d\n", rc);
+ else
+ pr_info("LCDB module successfully registered! lcdb_en=%d ldo_voltage=%dmV ncp_voltage=%dmV bst_voltage=%dmV\n",
+ lcdb->lcdb_enabled, lcdb->ldo.voltage_mv,
+ lcdb->ncp.voltage_mv, lcdb->bst.voltage_mv);
+
+ return rc;
+}
+
+static int qpnp_lcdb_regulator_remove(struct platform_device *pdev)
+{
+ struct qpnp_lcdb *lcdb = dev_get_drvdata(&pdev->dev);
+
+ mutex_destroy(&lcdb->lcdb_mutex);
+ mutex_destroy(&lcdb->read_write_mutex);
+
+ return 0;
+}
+
+static const struct of_device_id lcdb_match_table[] = {
+ { .compatible = QPNP_LCDB_REGULATOR_DRIVER_NAME, },
+ { },
+};
+
+static struct platform_driver qpnp_lcdb_regulator_driver = {
+ .driver = {
+ .name = QPNP_LCDB_REGULATOR_DRIVER_NAME,
+ .of_match_table = lcdb_match_table,
+ },
+ .probe = qpnp_lcdb_regulator_probe,
+ .remove = qpnp_lcdb_regulator_remove,
+};
+
+static int __init qpnp_lcdb_regulator_init(void)
+{
+ return platform_driver_register(&qpnp_lcdb_regulator_driver);
+}
+arch_initcall(qpnp_lcdb_regulator_init);
+
+static void __exit qpnp_lcdb_regulator_exit(void)
+{
+ platform_driver_unregister(&qpnp_lcdb_regulator_driver);
+}
+module_exit(qpnp_lcdb_regulator_exit);
+
+MODULE_DESCRIPTION("QPNP LCDB regulator driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/regulator/qpnp-oledb-regulator.c b/drivers/regulator/qpnp-oledb-regulator.c
new file mode 100644
index 0000000..8d017fb
--- /dev/null
+++ b/drivers/regulator/qpnp-oledb-regulator.c
@@ -0,0 +1,1201 @@
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "OLEDB: %s: " fmt, __func__
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+#include <linux/spmi.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/of_regulator.h>
+
+#define QPNP_OLEDB_REGULATOR_DRIVER_NAME "qcom,qpnp-oledb-regulator"
+#define OLEDB_VOUT_STEP_MV 100
+#define OLEDB_VOUT_MIN_MV 5000
+#define OLEDB_VOUT_MAX_MV 8100
+#define OLEDB_VOUT_HW_DEFAULT 6400
+
+#define OLEDB_MODULE_RDY 0x45
+#define OLEDB_MODULE_RDY_BIT BIT(7)
+
+#define OLEDB_MODULE_ENABLE 0x46
+#define OLEDB_MODULE_ENABLE_BIT BIT(7)
+
+#define OLEDB_EXT_PIN_CTL 0x47
+#define OLEDB_EXT_PIN_CTL_BIT BIT(7)
+
+#define OLEDB_SWIRE_CONTROL 0x48
+#define OLEDB_EN_SWIRE_VOUT_UPD_BIT BIT(6)
+#define OLEDB_EN_SWIRE_PD_UPD_BIT BIT(7)
+
+#define OLEDB_VOUT_PGM 0x49
+#define OLEDB_VOUT_PGM_MASK GENMASK(4, 0)
+
+#define OLEDB_VOUT_DEFAULT 0x4A
+#define OLEDB_VOUT_DEFAULT_MASK GENMASK(4, 0)
+
+#define OLEDB_PD_CTL 0x4B
+
+#define OLEDB_ILIM_NFET 0x4E
+#define OLEDB_ILIMIT_NFET_MASK GENMASK(2, 0)
+
+#define OLEDB_BIAS_GEN_WARMUP_DELAY 0x52
+#define OLEDB_BIAS_GEN_WARMUP_DELAY_MASK GENMASK(1, 0)
+
+#define OLEDB_SHORT_PROTECT 0x59
+#define OLEDB_ENABLE_SC_DETECTION_BIT BIT(7)
+#define OLEDB_DBNC_SHORT_DETECTION_MASK GENMASK(1, 0)
+
+#define OLEDB_FAST_PRECHARGE 0x5A
+#define OLEDB_FAST_PRECHG_PPULSE_EN_BIT BIT(7)
+#define OLEDB_DBNC_PRECHARGE_MASK GENMASK(5, 4)
+#define OLEDB_DBNC_PRECHARGE_SHIFT 4
+#define OLEDB_PRECHARGE_PULSE_PERIOD_MASK GENMASK(3, 2)
+#define OLEDB_PRECHARGE_PULSE_PERIOD_SHIFT 2
+#define OLEDB_PRECHARGE_PULSE_TON_MASK GENMASK(1, 0)
+
+#define OLEDB_EN_PSM 0x5B
+#define OLEDB_PSM_ENABLE_BIT BIT(7)
+
+#define OLEDB_PSM_CTL 0x5C
+#define OLEDB_PSM_HYSTERYSIS_CTL_BIT BIT(3)
+#define OLEDB_PSM_HYSTERYSIS_CTL_BIT_SHIFT 3
+#define OLEDB_VREF_PSM_MASK GENMASK(2, 0)
+
+#define OLEDB_PFM_CTL 0x5D
+#define OLEDB_PFM_ENABLE_BIT BIT(7)
+#define OLEDB_PFM_HYSTERYSIS_CTRL_BIT_MASK BIT(4)
+#define OLEDB_PFM_HYSTERYSIS_CTL_BIT_SHIFT 4
+#define OLEDB_PFM_CURR_LIMIT_MASK GENMASK(3, 2)
+#define OLEDB_PFM_CURR_LIMIT_SHIFT 2
+#define OLEDB_PFM_OFF_TIME_NS_MASK GENMASK(1, 0)
+
+#define OLEDB_NLIMIT 0x64
+#define OLEDB_ENABLE_NLIMIT_BIT BIT(7)
+#define OLEDB_ENABLE_NLIMIT_BIT_SHIFT 7
+#define OLEDB_NLIMIT_PGM_MASK GENMASK(1, 0)
+
+#define OLEDB_PSM_HYS_CTRL_MIN 13
+#define OLEDB_PSM_HYS_CTRL_MAX 26
+
+#define OLEDB_PFM_HYS_CTRL_MIN 13
+#define OLEDB_PFM_HYS_CTRL_MAX 26
+
+#define OLEDB_PFM_OFF_TIME_MIN 110
+#define OLEDB_PFM_OFF_TIME_MAX 480
+
+#define OLEDB_PRECHG_TIME_MIN 1
+#define OLEDB_PRECHG_TIME_MAX 8
+
+#define OLEDB_PRECHG_PULSE_PERIOD_MIN 3
+#define OLEDB_PRECHG_PULSE_PERIOD_MAX 12
+
+#define OLEDB_MIN_SC_DBNC_TIME_FSW 2
+#define OLEDB_MAX_SC_DBNC_TIME_FSW 16
+
+#define OLEDB_PRECHG_PULSE_ON_TIME_MIN 1200
+#define OLEDB_PRECHG_PULSE_ON_TIME_MAX 3000
+
+#define PSM_HYSTERYSIS_MV_TO_VAL(val_mv) ((val_mv/13) - 1)
+#define PFM_HYSTERYSIS_MV_TO_VAL(val_mv) ((val_mv/13) - 1)
+#define PFM_OFF_TIME_NS_TO_VAL(val_ns) ((val_ns/110) - 1)
+#define PRECHG_DEBOUNCE_TIME_MS_TO_VAL(val_ms) ((val_ms/2) - \
+ (val_ms/8))
+#define PRECHG_PULSE_PERIOD_US_TO_VAL(val_us) ((val_us/3) - 1)
+#define PRECHG_PULSE_ON_TIME_NS_TO_VAL(val_ns) (val_ns/600 - 2)
+#define SHORT_CIRCUIT_DEBOUNCE_TIME_TO_VAL(val) ((val/4) - (val/16))
+
+struct qpnp_oledb_psm_ctl {
+ int psm_enable;
+ int psm_hys_ctl;
+ int psm_vref;
+};
+
+struct qpnp_oledb_pfm_ctl {
+ int pfm_enable;
+ int pfm_hys_ctl;
+ int pfm_curr_limit;
+ int pfm_off_time;
+};
+
+struct qpnp_oledb_fast_precharge_ctl {
+ int fast_prechg_ppulse_en;
+ int prechg_debounce_time;
+ int prechg_pulse_period;
+ int prechg_pulse_on_time;
+};
+
+struct qpnp_oledb {
+ struct platform_device *pdev;
+ struct device *dev;
+ struct regmap *regmap;
+ struct regulator_desc rdesc;
+ struct regulator_dev *rdev;
+ struct qpnp_oledb_psm_ctl psm_ctl;
+ struct qpnp_oledb_pfm_ctl pfm_ctl;
+ struct qpnp_oledb_fast_precharge_ctl fast_prechg_ctl;
+
+ u32 base;
+ u8 mod_enable;
+ u8 ext_pinctl_state;
+ int current_voltage;
+ int default_voltage;
+ int vout_mv;
+ int warmup_delay;
+ int peak_curr_limit;
+ int pd_ctl;
+ int negative_curr_limit;
+ int nlimit_enable;
+ int sc_en;
+ int sc_dbnc_time;
+ bool swire_control;
+ bool ext_pin_control;
+ bool dynamic_ext_pinctl_config;
+ bool pbs_control;
+};
+
+static const u16 oledb_warmup_dly_ns[] = {6700, 13300, 26700, 53400};
+static const u16 oledb_peak_curr_limit_ma[] = {115, 265, 415, 570,
+ 720, 870, 1020, 1170};
+static const u16 oledb_psm_vref_mv[] = {440, 510, 580, 650, 715,
+ 780, 850, 920};
+static const u16 oledb_pfm_curr_limit_ma[] = {130, 200, 270, 340};
+static const u16 oledb_nlimit_ma[] = {170, 300, 420, 550};
+
+static int qpnp_oledb_read(struct qpnp_oledb *oledb, u32 address,
+ u8 *val, int count)
+{
+ int rc = 0;
+ struct platform_device *pdev = oledb->pdev;
+
+ rc = regmap_bulk_read(oledb->regmap, address, val, count);
+ if (rc)
+ pr_err("Failed to read address=0x%02x sid=0x%02x rc=%d\n",
+ address, to_spmi_device(pdev->dev.parent)->usid, rc);
+
+ return rc;
+}
+
+static int qpnp_oledb_masked_write(struct qpnp_oledb *oledb,
+ u32 address, u8 mask, u8 val)
+{
+ int rc;
+
+ rc = regmap_update_bits(oledb->regmap, address, mask, val);
+ if (rc < 0)
+ pr_err("Failed to write address 0x%04X, rc = %d\n",
+ address, rc);
+ else
+ pr_debug("Wrote 0x%02X to addr 0x%04X\n",
+ val, address);
+
+ return rc;
+}
+
+static int qpnp_oledb_write(struct qpnp_oledb *oledb, u16 address, u8 *val,
+ int count)
+{
+ int rc = 0;
+ struct platform_device *pdev = oledb->pdev;
+
+ rc = regmap_bulk_write(oledb->regmap, address, val, count);
+ if (rc)
+ pr_err("Failed to write address=0x%02x sid=0x%02x rc=%d\n",
+ address, to_spmi_device(pdev->dev.parent)->usid, rc);
+ else
+ pr_debug("Wrote 0x%02X to addr 0x%04X\n",
+ *val, address);
+
+ return 0;
+}
+
+static int qpnp_oledb_regulator_enable(struct regulator_dev *rdev)
+{
+ int rc = 0;
+ u8 val = 0;
+
+ struct qpnp_oledb *oledb = rdev_get_drvdata(rdev);
+
+ if (oledb->ext_pin_control) {
+ rc = qpnp_oledb_read(oledb, oledb->base + OLEDB_EXT_PIN_CTL,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to read EXT_PIN_CTL rc=%d\n", rc);
+ return rc;
+ }
+
+ /*
+ * Enable ext-pin-ctl after display-supply is turned on.
+ * This is to avoid glitches on the external pin.
+ */
+ if (!(val & OLEDB_EXT_PIN_CTL_BIT) &&
+ oledb->dynamic_ext_pinctl_config) {
+ val = OLEDB_EXT_PIN_CTL_BIT;
+ rc = qpnp_oledb_write(oledb, oledb->base +
+ OLEDB_EXT_PIN_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to write EXT_PIN_CTL rc=%d\n",
+ rc);
+ return rc;
+ }
+ }
+ pr_debug("ext-pin-ctrl mode enabled\n");
+ } else {
+ val = OLEDB_MODULE_ENABLE_BIT;
+ rc = qpnp_oledb_write(oledb, oledb->base + OLEDB_MODULE_ENABLE,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to write MODULE_ENABLE rc=%d\n", rc);
+ return rc;
+ }
+
+ ndelay(oledb->warmup_delay);
+ pr_debug("register-control mode, module enabled\n");
+ }
+
+ oledb->mod_enable = true;
+ if (oledb->pbs_control) {
+ rc = qpnp_oledb_masked_write(oledb, oledb->base +
+ OLEDB_SWIRE_CONTROL, OLEDB_EN_SWIRE_PD_UPD_BIT |
+ OLEDB_EN_SWIRE_VOUT_UPD_BIT, 0);
+ if (rc < 0)
+ pr_err("Failed to write SWIRE_CTL for pbs mode rc=%d\n",
+ rc);
+ }
+
+ return rc;
+}
+
+static int qpnp_oledb_regulator_disable(struct regulator_dev *rdev)
+{
+ int rc = 0;
+
+ struct qpnp_oledb *oledb = rdev_get_drvdata(rdev);
+
+ /*
+ * Disable ext-pin-ctl after display-supply is turned off. This is to
+ * avoid glitches on the external pin.
+ */
+ if (oledb->ext_pin_control) {
+ if (oledb->dynamic_ext_pinctl_config) {
+ rc = qpnp_oledb_masked_write(oledb, oledb->base +
+ OLEDB_EXT_PIN_CTL, OLEDB_EXT_PIN_CTL_BIT, 0);
+ if (rc < 0) {
+ pr_err("Failed to write EXT_PIN_CTL rc=%d\n",
+ rc);
+ return rc;
+ }
+ }
+ pr_debug("ext-pin-ctrl mode disabled\n");
+ } else {
+ rc = qpnp_oledb_masked_write(oledb, oledb->base +
+ OLEDB_MODULE_ENABLE,
+ OLEDB_MODULE_ENABLE_BIT, 0);
+ if (rc < 0) {
+ pr_err("Failed to write MODULE_ENABLE rc=%d\n", rc);
+ return rc;
+ }
+ pr_debug("Register-control mode, module disabled\n");
+ }
+
+ oledb->mod_enable = false;
+
+ return rc;
+}
+
+static int qpnp_oledb_regulator_is_enabled(struct regulator_dev *rdev)
+{
+ struct qpnp_oledb *oledb = rdev_get_drvdata(rdev);
+
+ return oledb->mod_enable;
+}
+
+static int qpnp_oledb_regulator_set_voltage(struct regulator_dev *rdev,
+ int min_uV, int max_uV, unsigned int *selector)
+{
+ u8 val;
+ int rc = 0;
+
+ struct qpnp_oledb *oledb = rdev_get_drvdata(rdev);
+
+ if (oledb->swire_control)
+ return 0;
+
+ val = DIV_ROUND_UP(min_uV - OLEDB_VOUT_MIN_MV, OLEDB_VOUT_STEP_MV);
+
+ rc = qpnp_oledb_write(oledb, oledb->base + OLEDB_VOUT_PGM,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to write VOUT_PGM rc=%d\n", rc);
+ return rc;
+ }
+
+ oledb->current_voltage = min_uV;
+ pr_debug("register-control mode, current voltage %d\n",
+ oledb->current_voltage);
+
+ return 0;
+}
+
+static int qpnp_oledb_regulator_get_voltage(struct regulator_dev *rdev)
+{
+ struct qpnp_oledb *oledb = rdev_get_drvdata(rdev);
+
+ if (oledb->swire_control)
+ return 0;
+
+ return oledb->current_voltage;
+}
+
+static struct regulator_ops qpnp_oledb_ops = {
+ .enable = qpnp_oledb_regulator_enable,
+ .disable = qpnp_oledb_regulator_disable,
+ .is_enabled = qpnp_oledb_regulator_is_enabled,
+ .set_voltage = qpnp_oledb_regulator_set_voltage,
+ .get_voltage = qpnp_oledb_regulator_get_voltage,
+};
+
+static int qpnp_oledb_register_regulator(struct qpnp_oledb *oledb)
+{
+ int rc = 0;
+ struct platform_device *pdev = oledb->pdev;
+ struct regulator_init_data *init_data;
+ struct regulator_desc *rdesc = &oledb->rdesc;
+ struct regulator_config cfg = {};
+
+ init_data = of_get_regulator_init_data(&pdev->dev,
+ pdev->dev.of_node, rdesc);
+ if (!init_data) {
+ pr_err("Unable to get OLEDB regulator init data\n");
+ return -ENOMEM;
+ }
+
+ if (init_data->constraints.name) {
+ rdesc->owner = THIS_MODULE;
+ rdesc->type = REGULATOR_VOLTAGE;
+ rdesc->ops = &qpnp_oledb_ops;
+ rdesc->name = init_data->constraints.name;
+
+ cfg.dev = &pdev->dev;
+ cfg.init_data = init_data;
+ cfg.driver_data = oledb;
+ cfg.of_node = pdev->dev.of_node;
+
+ if (of_get_property(pdev->dev.of_node, "parent-supply",
+ NULL))
+ init_data->supply_regulator = "parent";
+
+ init_data->constraints.valid_ops_mask
+ |= REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS;
+
+ oledb->rdev = devm_regulator_register(oledb->dev, rdesc, &cfg);
+ if (IS_ERR(oledb->rdev)) {
+ rc = PTR_ERR(oledb->rdev);
+ oledb->rdev = NULL;
+ pr_err("Unable to register OLEDB regulator, rc = %d\n",
+ rc);
+ return rc;
+ }
+ } else {
+ pr_err("OLEDB regulator name missing\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int qpnp_oledb_get_curr_voltage(struct qpnp_oledb *oledb,
+ u16 *current_voltage)
+{
+ int rc = 0;
+ u8 val;
+
+ if (!(oledb->mod_enable || oledb->ext_pinctl_state)) {
+ rc = qpnp_oledb_read(oledb, oledb->base + OLEDB_VOUT_DEFAULT,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to read VOUT_DEFAULT rc=%d\n", rc);
+ return rc;
+ }
+ } else {
+ rc = qpnp_oledb_read(oledb, oledb->base +
+ OLEDB_VOUT_PGM, &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to read VOUT_PGM rc=%d\n", rc);
+ return rc;
+ }
+ }
+
+ *current_voltage = (val * OLEDB_VOUT_STEP_MV) + OLEDB_VOUT_MIN_MV;
+
+ return rc;
+}
+
+static int qpnp_oledb_init_nlimit(struct qpnp_oledb *oledb)
+{
+ int rc = 0, i = 0;
+ u32 val, mask = 0;
+
+ if (oledb->nlimit_enable != -EINVAL) {
+ val = oledb->nlimit_enable <<
+ OLEDB_ENABLE_NLIMIT_BIT_SHIFT;
+ mask = OLEDB_ENABLE_NLIMIT_BIT;
+ if (oledb->negative_curr_limit != -EINVAL) {
+ for (i = 0; i < ARRAY_SIZE(oledb_nlimit_ma); i++) {
+ if (oledb->negative_curr_limit ==
+ oledb_nlimit_ma[i])
+ break;
+ }
+ val |= i;
+ mask |= OLEDB_NLIMIT_PGM_MASK;
+ }
+ rc = qpnp_oledb_masked_write(oledb, oledb->base +
+ OLEDB_NLIMIT, mask, val);
+ if (rc < 0)
+ pr_err("Failed to write NLIMT rc=%d\n", rc);
+ }
+
+ return rc;
+}
+
+static int qpnp_oledb_init_psm(struct qpnp_oledb *oledb)
+{
+ int rc = 0, i = 0;
+ u32 val = 0, mask = 0, temp = 0;
+ struct qpnp_oledb_psm_ctl *psm_ctl = &oledb->psm_ctl;
+
+ if (psm_ctl->psm_enable == -EINVAL)
+ return rc;
+
+ if (psm_ctl->psm_enable) {
+ val = OLEDB_PSM_ENABLE_BIT;
+ rc = qpnp_oledb_masked_write(oledb, oledb->base +
+ OLEDB_EN_PSM, OLEDB_PSM_ENABLE_BIT, val);
+ if (rc < 0) {
+ pr_err("Failed to write PSM_EN rc=%d\n", rc);
+ return rc;
+ }
+
+ val = 0;
+ if (psm_ctl->psm_vref != -EINVAL) {
+ for (i = 0; i < ARRAY_SIZE(oledb_psm_vref_mv); i++) {
+ if (psm_ctl->psm_vref ==
+ oledb_psm_vref_mv[i])
+ break;
+ }
+ val = i;
+ mask = OLEDB_VREF_PSM_MASK;
+ }
+
+ if (psm_ctl->psm_hys_ctl != -EINVAL) {
+ temp = PSM_HYSTERYSIS_MV_TO_VAL(psm_ctl->psm_hys_ctl);
+ val |= (temp << OLEDB_PSM_HYSTERYSIS_CTL_BIT_SHIFT);
+ mask |= OLEDB_PSM_HYSTERYSIS_CTL_BIT;
+ }
+ if (val) {
+ rc = qpnp_oledb_masked_write(oledb, oledb->base +
+ OLEDB_PSM_CTL, mask, val);
+ if (rc < 0)
+ pr_err("Failed to write PSM_CTL rc=%d\n", rc);
+ }
+ } else {
+ rc = qpnp_oledb_masked_write(oledb, oledb->base +
+ OLEDB_EN_PSM, OLEDB_PSM_ENABLE_BIT, 0);
+ if (rc < 0)
+ pr_err("Failed to write PSM_CTL rc=%d\n", rc);
+ }
+
+ return rc;
+}
+
+static int qpnp_oledb_init_pfm(struct qpnp_oledb *oledb)
+{
+ int rc = 0, i = 0;
+ u32 val = 0, temp = 0, mask = 0;
+ struct qpnp_oledb_pfm_ctl *pfm_ctl = &oledb->pfm_ctl;
+
+ if (pfm_ctl->pfm_enable == -EINVAL)
+ return rc;
+
+ if (pfm_ctl->pfm_enable) {
+ mask = val = OLEDB_PFM_ENABLE_BIT;
+ if (pfm_ctl->pfm_hys_ctl != -EINVAL) {
+ temp = PFM_HYSTERYSIS_MV_TO_VAL(pfm_ctl->pfm_hys_ctl);
+ val |= temp <<
+ OLEDB_PFM_HYSTERYSIS_CTL_BIT_SHIFT;
+ mask |= OLEDB_PFM_HYSTERYSIS_CTRL_BIT_MASK;
+ }
+
+ if (pfm_ctl->pfm_curr_limit != -EINVAL) {
+ for (i = 0; i < ARRAY_SIZE(oledb_pfm_curr_limit_ma);
+ i++) {
+ if (pfm_ctl->pfm_curr_limit ==
+ oledb_pfm_curr_limit_ma[i])
+ break;
+ }
+ val |= (i << OLEDB_PFM_CURR_LIMIT_SHIFT);
+ mask |= OLEDB_PFM_CURR_LIMIT_MASK;
+ }
+
+ if (pfm_ctl->pfm_off_time != -EINVAL) {
+ val |= PFM_OFF_TIME_NS_TO_VAL(pfm_ctl->pfm_off_time);
+ mask |= OLEDB_PFM_OFF_TIME_NS_MASK;
+ }
+
+ rc = qpnp_oledb_masked_write(oledb, oledb->base +
+ OLEDB_PFM_CTL, mask, val);
+ if (rc < 0)
+ pr_err("Failed to write PFM_CTL rc=%d\n", rc);
+ } else {
+ rc = qpnp_oledb_masked_write(oledb, oledb->base +
+ OLEDB_PFM_CTL, OLEDB_PFM_ENABLE_BIT, 0);
+ if (rc < 0)
+ pr_err("Failed to write PFM_CTL rc=%d\n", rc);
+ }
+
+ return rc;
+}
+
+static int qpnp_oledb_init_fast_precharge(struct qpnp_oledb *oledb)
+{
+ int rc = 0;
+ u32 val = 0, temp = 0, mask = 0;
+ struct qpnp_oledb_fast_precharge_ctl *prechg_ctl =
+ &oledb->fast_prechg_ctl;
+
+ if (prechg_ctl->fast_prechg_ppulse_en == -EINVAL)
+ return rc;
+
+ if (prechg_ctl->fast_prechg_ppulse_en) {
+ mask = val = OLEDB_FAST_PRECHG_PPULSE_EN_BIT;
+ if (prechg_ctl->prechg_debounce_time != -EINVAL) {
+ temp = PRECHG_DEBOUNCE_TIME_MS_TO_VAL(
+ prechg_ctl->prechg_debounce_time);
+ val |= temp << OLEDB_DBNC_PRECHARGE_SHIFT;
+ mask |= OLEDB_DBNC_PRECHARGE_MASK;
+ }
+
+ if (prechg_ctl->prechg_pulse_period != -EINVAL) {
+ temp = PRECHG_PULSE_PERIOD_US_TO_VAL(
+ prechg_ctl->prechg_pulse_period);
+ val |= temp << OLEDB_PRECHARGE_PULSE_PERIOD_SHIFT;
+ mask |= OLEDB_PRECHARGE_PULSE_PERIOD_MASK;
+ }
+
+ if (prechg_ctl->prechg_pulse_on_time != -EINVAL) {
+ val |= PRECHG_PULSE_ON_TIME_NS_TO_VAL(
+ prechg_ctl->prechg_pulse_on_time);
+ mask |= OLEDB_PRECHARGE_PULSE_TON_MASK;
+ }
+
+ rc = qpnp_oledb_masked_write(oledb, oledb->base +
+ OLEDB_FAST_PRECHARGE, mask, val);
+ if (rc < 0)
+ pr_err("Failed to write FAST_PRECHARGE rc=%d\n", rc);
+ } else {
+ rc = qpnp_oledb_masked_write(oledb, oledb->base +
+ OLEDB_FAST_PRECHARGE,
+ OLEDB_FAST_PRECHG_PPULSE_EN_BIT, 0);
+ if (rc < 0)
+ pr_err("Failed to write FAST_PRECHARGE rc=%d\n", rc);
+ }
+
+ return rc;
+}
+
+static int qpnp_oledb_hw_init(struct qpnp_oledb *oledb)
+{
+ int rc, i = 0;
+ u8 val = 0, mask = 0;
+ u16 current_voltage;
+
+ if (oledb->default_voltage != -EINVAL) {
+ val = (oledb->default_voltage - OLEDB_VOUT_MIN_MV) /
+ OLEDB_VOUT_STEP_MV;
+ rc = qpnp_oledb_write(oledb, oledb->base +
+ OLEDB_VOUT_DEFAULT, &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to write VOUT_DEFAULT rc=%d\n", rc);
+ return rc;
+ }
+ }
+
+ rc = qpnp_oledb_read(oledb, oledb->base + OLEDB_MODULE_ENABLE,
+ &oledb->mod_enable, 1);
+ if (rc < 0) {
+ pr_err("Failed to read MODULE_ENABLE rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = qpnp_oledb_read(oledb, oledb->base + OLEDB_EXT_PIN_CTL,
+ &oledb->ext_pinctl_state, 1);
+ if (rc < 0) {
+ pr_err("Failed to read EXT_PIN_CTL rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = qpnp_oledb_get_curr_voltage(oledb, ¤t_voltage);
+ if (rc < 0)
+ return rc;
+
+ /*
+ * Go through if the module is not enabled either through
+ * external pin control or SPMI interface.
+ */
+ if (!((oledb->ext_pinctl_state & OLEDB_EXT_PIN_CTL_BIT)
+ || oledb->mod_enable)) {
+ if (oledb->warmup_delay != -EINVAL) {
+ for (i = 0; i < ARRAY_SIZE(oledb_warmup_dly_ns); i++) {
+ if (oledb->warmup_delay ==
+ oledb_warmup_dly_ns[i])
+ break;
+ }
+ val = i;
+ rc = qpnp_oledb_masked_write(oledb,
+ oledb->base + OLEDB_BIAS_GEN_WARMUP_DELAY,
+ OLEDB_BIAS_GEN_WARMUP_DELAY_MASK, val);
+ if (rc < 0) {
+ pr_err("Failed to write WARMUP_DELAY rc=%d\n",
+ rc);
+ return rc;
+ }
+ } else {
+ rc = qpnp_oledb_read(oledb, oledb->base +
+ OLEDB_BIAS_GEN_WARMUP_DELAY,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to read WARMUP_DELAY rc=%d\n",
+ rc);
+ return rc;
+ }
+ oledb->warmup_delay = oledb_warmup_dly_ns[val];
+ }
+
+ if (oledb->peak_curr_limit != -EINVAL) {
+ for (i = 0; i < ARRAY_SIZE(oledb_peak_curr_limit_ma);
+ i++) {
+ if (oledb->peak_curr_limit ==
+ oledb_peak_curr_limit_ma[i])
+ break;
+ }
+ val = i;
+ rc = qpnp_oledb_write(oledb,
+ oledb->base + OLEDB_ILIM_NFET,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to write ILIM_NEFT rc=%d\n", rc);
+ return rc;
+ }
+ }
+
+ if (oledb->pd_ctl != -EINVAL) {
+ val = oledb->pd_ctl;
+ rc = qpnp_oledb_write(oledb, oledb->base +
+ OLEDB_PD_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to write PD_CTL rc=%d\n", rc);
+ return rc;
+ }
+ }
+
+ if (oledb->sc_en != -EINVAL) {
+ val = oledb->sc_en ? OLEDB_ENABLE_SC_DETECTION_BIT : 0;
+ mask = OLEDB_ENABLE_SC_DETECTION_BIT;
+ if (oledb->sc_dbnc_time != -EINVAL) {
+ val |= SHORT_CIRCUIT_DEBOUNCE_TIME_TO_VAL(
+ oledb->sc_dbnc_time);
+ mask |= OLEDB_DBNC_PRECHARGE_MASK;
+ }
+
+ rc = qpnp_oledb_write(oledb, oledb->base +
+ OLEDB_SHORT_PROTECT, &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to write SHORT_PROTECT rc=%d\n",
+ rc);
+ return rc;
+ }
+ }
+
+ rc = qpnp_oledb_init_nlimit(oledb);
+ if (rc < 0)
+ return rc;
+
+ rc = qpnp_oledb_init_psm(oledb);
+ if (rc < 0)
+ return rc;
+
+ rc = qpnp_oledb_init_pfm(oledb);
+ if (rc < 0)
+ return rc;
+
+ rc = qpnp_oledb_init_fast_precharge(oledb);
+ if (rc < 0)
+ return rc;
+
+ if (oledb->swire_control) {
+ val = OLEDB_EN_SWIRE_PD_UPD_BIT |
+ OLEDB_EN_SWIRE_VOUT_UPD_BIT;
+ rc = qpnp_oledb_masked_write(oledb, oledb->base +
+ OLEDB_SWIRE_CONTROL, OLEDB_EN_SWIRE_PD_UPD_BIT |
+ OLEDB_EN_SWIRE_VOUT_UPD_BIT, val);
+ if (rc < 0)
+ return rc;
+ }
+
+ rc = qpnp_oledb_read(oledb, oledb->base + OLEDB_MODULE_RDY,
+ &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to read MODULE_RDY rc=%d\n", rc);
+ return rc;
+ }
+
+ if (!(val & OLEDB_MODULE_RDY_BIT)) {
+ val = OLEDB_MODULE_RDY_BIT;
+ rc = qpnp_oledb_write(oledb, oledb->base +
+ OLEDB_MODULE_RDY, &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to write MODULE_RDY rc=%d\n",
+ rc);
+ return rc;
+ }
+ }
+
+ if (!oledb->dynamic_ext_pinctl_config) {
+ if (oledb->ext_pin_control) {
+ val = OLEDB_EXT_PIN_CTL_BIT;
+ rc = qpnp_oledb_write(oledb, oledb->base +
+ OLEDB_EXT_PIN_CTL, &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to write EXT_PIN_CTL rc=%d\n",
+ rc);
+ return rc;
+ }
+ } else {
+ val = OLEDB_MODULE_ENABLE_BIT;
+ rc = qpnp_oledb_write(oledb, oledb->base +
+ OLEDB_MODULE_ENABLE, &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to write MODULE_ENABLE rc=%d\n",
+ rc);
+ return rc;
+ }
+
+ ndelay(oledb->warmup_delay);
+ }
+
+ oledb->mod_enable = true;
+ if (oledb->pbs_control) {
+ rc = qpnp_oledb_masked_write(oledb,
+ oledb->base + OLEDB_SWIRE_CONTROL,
+ OLEDB_EN_SWIRE_PD_UPD_BIT |
+ OLEDB_EN_SWIRE_VOUT_UPD_BIT, 0);
+ if (rc < 0) {
+ pr_err("Failed to write SWIRE_CTL rc=%d\n",
+ rc);
+ return rc;
+ }
+ }
+ }
+
+ oledb->current_voltage = current_voltage;
+ } else {
+ /* module is enabled */
+ if (oledb->current_voltage == -EINVAL) {
+ oledb->current_voltage = current_voltage;
+ } else if (!oledb->swire_control) {
+ if (oledb->current_voltage < OLEDB_VOUT_MIN_MV) {
+ pr_err("current_voltage %d is less than min_volt %d\n",
+ oledb->current_voltage, OLEDB_VOUT_MIN_MV);
+ return -EINVAL;
+ }
+ val = DIV_ROUND_UP(oledb->current_voltage -
+ OLEDB_VOUT_MIN_MV, OLEDB_VOUT_STEP_MV);
+ rc = qpnp_oledb_write(oledb, oledb->base +
+ OLEDB_VOUT_PGM, &val, 1);
+ if (rc < 0) {
+ pr_err("Failed to write VOUT_PGM rc=%d\n",
+ rc);
+ return rc;
+ }
+ }
+
+ oledb->mod_enable = true;
+ }
+
+ return rc;
+}
+
+static int qpnp_oledb_parse_nlimit(struct qpnp_oledb *oledb)
+{
+ int rc = 0;
+ struct device_node *of_node = oledb->dev->of_node;
+
+ oledb->nlimit_enable = -EINVAL;
+ rc = of_property_read_u32(of_node, "qcom,negative-curr-limit-enable",
+ &oledb->nlimit_enable);
+ if (!rc) {
+ oledb->negative_curr_limit = -EINVAL;
+ rc = of_property_read_u32(of_node,
+ "qcom,negative-curr-limit-ma",
+ &oledb->negative_curr_limit);
+ if (!rc) {
+ u16 min_curr_limit = oledb_nlimit_ma[0];
+ u16 max_curr_limit = oledb_nlimit_ma[ARRAY_SIZE(
+ oledb_nlimit_ma) - 1];
+ if (oledb->negative_curr_limit < min_curr_limit ||
+ oledb->negative_curr_limit > max_curr_limit) {
+ pr_err("Invalid value in qcom,negative-curr-limit-ma\n");
+ return -EINVAL;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int qpnp_oledb_parse_psm(struct qpnp_oledb *oledb)
+{
+ int rc = 0;
+ struct qpnp_oledb_psm_ctl *psm_ctl = &oledb->psm_ctl;
+ struct device_node *of_node = oledb->dev->of_node;
+
+ psm_ctl->psm_enable = -EINVAL;
+ rc = of_property_read_u32(of_node, "qcom,psm-enable",
+ &psm_ctl->psm_enable);
+ if (!rc) {
+ psm_ctl->psm_hys_ctl = -EINVAL;
+ rc = of_property_read_u32(of_node, "qcom,psm-hys-mv",
+ &psm_ctl->psm_hys_ctl);
+ if (!rc) {
+ if (psm_ctl->psm_hys_ctl < OLEDB_PSM_HYS_CTRL_MIN ||
+ psm_ctl->psm_hys_ctl > OLEDB_PSM_HYS_CTRL_MAX) {
+ pr_err("Invalid value in qcom,psm-hys-mv\n");
+ return -EINVAL;
+ }
+ }
+
+ psm_ctl->psm_vref = -EINVAL;
+ rc = of_property_read_u32(of_node, "qcom,psm-vref-mv",
+ &psm_ctl->psm_vref);
+ if (!rc) {
+ u16 min_vref = oledb_psm_vref_mv[0];
+ u16 max_vref = oledb_psm_vref_mv[ARRAY_SIZE(
+ oledb_psm_vref_mv) - 1];
+ if (psm_ctl->psm_vref < min_vref ||
+ psm_ctl->psm_vref > max_vref) {
+ pr_err("Invalid value in qcom,psm-vref-mv\n");
+ return -EINVAL;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int qpnp_oledb_parse_pfm(struct qpnp_oledb *oledb)
+{
+ int rc = 0;
+ struct qpnp_oledb_pfm_ctl *pfm_ctl = &oledb->pfm_ctl;
+ struct device_node *of_node = oledb->dev->of_node;
+
+ pfm_ctl->pfm_enable = -EINVAL;
+ rc = of_property_read_u32(of_node, "qcom,pfm-enable",
+ &pfm_ctl->pfm_enable);
+ if (!rc) {
+ pfm_ctl->pfm_hys_ctl = -EINVAL;
+ rc = of_property_read_u32(of_node, "qcom,pfm-hys-mv",
+ &pfm_ctl->pfm_hys_ctl);
+ if (!rc) {
+ if (pfm_ctl->pfm_hys_ctl < OLEDB_PFM_HYS_CTRL_MIN ||
+ pfm_ctl->pfm_hys_ctl > OLEDB_PFM_HYS_CTRL_MAX) {
+ pr_err("Invalid value in qcom,pfm-hys-mv\n");
+ return -EINVAL;
+ }
+ }
+
+ pfm_ctl->pfm_curr_limit = -EINVAL;
+ rc = of_property_read_u32(of_node,
+ "qcom,pfm-curr-limit-ma", &pfm_ctl->pfm_curr_limit);
+ if (!rc) {
+ u16 min_limit = oledb_pfm_curr_limit_ma[0];
+ u16 max_limit = oledb_pfm_curr_limit_ma[ARRAY_SIZE(
+ oledb_pfm_curr_limit_ma) - 1];
+ if (pfm_ctl->pfm_curr_limit < min_limit ||
+ pfm_ctl->pfm_curr_limit > max_limit) {
+ pr_err("Invalid value in qcom,pfm-curr-limit-ma\n");
+ return -EINVAL;
+ }
+ }
+
+ pfm_ctl->pfm_off_time = -EINVAL;
+ rc = of_property_read_u32(of_node, "qcom,pfm-off-time-ns",
+ &pfm_ctl->pfm_off_time);
+ if (!rc) {
+ if (pfm_ctl->pfm_off_time < OLEDB_PFM_OFF_TIME_MIN ||
+ pfm_ctl->pfm_off_time > OLEDB_PFM_OFF_TIME_MAX) {
+ pr_err("Invalid value in qcom,pfm-off-time-ns\n");
+ return -EINVAL;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int qpnp_oledb_parse_fast_precharge(struct qpnp_oledb *oledb)
+{
+ int rc = 0;
+ struct device_node *of_node = oledb->dev->of_node;
+ struct qpnp_oledb_fast_precharge_ctl *fast_prechg =
+ &oledb->fast_prechg_ctl;
+
+ fast_prechg->fast_prechg_ppulse_en = -EINVAL;
+ rc = of_property_read_u32(of_node, "qcom,fast-precharge-ppulse-enable",
+ &fast_prechg->fast_prechg_ppulse_en);
+ if (!rc) {
+ fast_prechg->prechg_debounce_time = -EINVAL;
+ rc = of_property_read_u32(of_node,
+ "qcom,precharge-debounce-time-ms",
+ &fast_prechg->prechg_debounce_time);
+ if (!rc) {
+ int dbnc_time = fast_prechg->prechg_debounce_time;
+
+ if (dbnc_time < OLEDB_PRECHG_TIME_MIN || dbnc_time >
+ OLEDB_PRECHG_TIME_MAX) {
+ pr_err("Invalid value in qcom,precharge-debounce-time-ms\n");
+ return -EINVAL;
+ }
+ }
+
+ fast_prechg->prechg_pulse_period = -EINVAL;
+ rc = of_property_read_u32(of_node,
+ "qcom,precharge-pulse-period-us",
+ &fast_prechg->prechg_pulse_period);
+ if (!rc) {
+ int pulse_period = fast_prechg->prechg_pulse_period;
+
+ if (pulse_period < OLEDB_PRECHG_PULSE_PERIOD_MIN ||
+ pulse_period > OLEDB_PRECHG_PULSE_PERIOD_MAX) {
+ pr_err("Invalid value in qcom,precharge-pulse-period-us\n");
+ return -EINVAL;
+ }
+ }
+
+ fast_prechg->prechg_pulse_on_time = -EINVAL;
+ rc = of_property_read_u32(of_node,
+ "qcom,precharge-pulse-on-time-ns",
+ &fast_prechg->prechg_pulse_on_time);
+ if (!rc) {
+ int pulse_on_time = fast_prechg->prechg_pulse_on_time;
+
+ if (pulse_on_time < OLEDB_PRECHG_PULSE_ON_TIME_MIN ||
+ pulse_on_time > OLEDB_PRECHG_PULSE_ON_TIME_MAX) {
+ pr_err("Invalid value in qcom,precharge-pulse-on-time-ns\n");
+ return -EINVAL;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int qpnp_oledb_parse_dt(struct qpnp_oledb *oledb)
+{
+ int rc = 0;
+ struct device_node *of_node = oledb->dev->of_node;
+
+ oledb->swire_control =
+ of_property_read_bool(of_node, "qcom,swire-control");
+
+ oledb->ext_pin_control =
+ of_property_read_bool(of_node, "qcom,ext-pin-control");
+
+ if (oledb->ext_pin_control)
+ oledb->dynamic_ext_pinctl_config =
+ of_property_read_bool(of_node,
+ "qcom,dynamic-ext-pinctl-config");
+ oledb->pbs_control =
+ of_property_read_bool(of_node, "qcom,pbs-control");
+
+ oledb->current_voltage = -EINVAL;
+ rc = of_property_read_u32(of_node, "qcom,oledb-init-voltage-mv",
+ &oledb->current_voltage);
+ if (!rc && (oledb->current_voltage < OLEDB_VOUT_MIN_MV ||
+ oledb->current_voltage > OLEDB_VOUT_MAX_MV)) {
+ pr_err("Invalid value in qcom,oledb-init-voltage-mv\n");
+ return -EINVAL;
+ }
+
+ oledb->default_voltage = -EINVAL;
+ rc = of_property_read_u32(of_node, "qcom,oledb-default-voltage-mv",
+ &oledb->default_voltage);
+ if (!rc && (oledb->default_voltage < OLEDB_VOUT_MIN_MV ||
+ oledb->default_voltage > OLEDB_VOUT_MAX_MV)) {
+ pr_err("Invalid value in qcom,oledb-default-voltage-mv\n");
+ return -EINVAL;
+ }
+
+ oledb->warmup_delay = -EINVAL;
+ rc = of_property_read_u32(of_node, "qcom,bias-gen-warmup-delay-ns",
+ &oledb->warmup_delay);
+ if (!rc) {
+ u16 min_delay = oledb_warmup_dly_ns[0];
+ u16 max_delay = oledb_warmup_dly_ns[ARRAY_SIZE(
+ oledb_warmup_dly_ns) - 1];
+ if (oledb->warmup_delay < min_delay ||
+ oledb->warmup_delay > max_delay) {
+ pr_err("Invalid value in qcom,bias-gen-warmup-delay-ns\n");
+ return -EINVAL;
+ }
+ }
+
+ oledb->peak_curr_limit = -EINVAL;
+ rc = of_property_read_u32(of_node, "qcom,peak-curr-limit-ma",
+ &oledb->peak_curr_limit);
+ if (!rc) {
+ u16 min_limit = oledb_peak_curr_limit_ma[0];
+ u16 max_limit = oledb_peak_curr_limit_ma[ARRAY_SIZE(
+ oledb_peak_curr_limit_ma) - 1];
+ if (oledb->peak_curr_limit < min_limit ||
+ oledb->peak_curr_limit > max_limit) {
+ pr_err("Invalid value in qcom,peak-curr-limit-ma\n");
+ return -EINVAL;
+ }
+ }
+
+ oledb->pd_ctl = -EINVAL;
+ of_property_read_u32(of_node, "qcom,pull-down-enable", &oledb->pd_ctl);
+
+ oledb->sc_en = -EINVAL;
+ rc = of_property_read_u32(of_node, "qcom,enable-short-circuit",
+ &oledb->sc_en);
+ if (!rc) {
+ oledb->sc_dbnc_time = -EINVAL;
+ rc = of_property_read_u32(of_node,
+ "qcom,short-circuit-dbnc-time", &oledb->sc_dbnc_time);
+ if (!rc) {
+ if (oledb->sc_dbnc_time < OLEDB_MIN_SC_DBNC_TIME_FSW ||
+ oledb->sc_dbnc_time > OLEDB_MAX_SC_DBNC_TIME_FSW) {
+ pr_err("Invalid value in qcom,short-circuit-dbnc-time\n");
+ return -EINVAL;
+ }
+ }
+ }
+
+ rc = qpnp_oledb_parse_nlimit(oledb);
+ if (rc < 0)
+ return rc;
+
+ rc = qpnp_oledb_parse_psm(oledb);
+ if (rc < 0)
+ return rc;
+
+ rc = qpnp_oledb_parse_pfm(oledb);
+ if (rc < 0)
+ return rc;
+
+ rc = qpnp_oledb_parse_fast_precharge(oledb);
+
+ return rc;
+}
+
+static int qpnp_oledb_regulator_probe(struct platform_device *pdev)
+{
+ int rc = 0;
+ u32 val;
+ struct qpnp_oledb *oledb;
+ struct device_node *of_node = pdev->dev.of_node;
+
+ oledb = devm_kzalloc(&pdev->dev,
+ sizeof(struct qpnp_oledb), GFP_KERNEL);
+ if (!oledb)
+ return -ENOMEM;
+
+ oledb->pdev = pdev;
+ oledb->dev = &pdev->dev;
+ oledb->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ dev_set_drvdata(&pdev->dev, oledb);
+ if (!oledb->regmap) {
+ pr_err("Couldn't get parent's regmap\n");
+ return -EINVAL;
+ }
+
+ rc = of_property_read_u32(of_node, "reg", &val);
+ if (rc < 0) {
+ pr_err("Couldn't find reg in node, rc = %d\n", rc);
+ return rc;
+ }
+
+ oledb->base = val;
+ rc = qpnp_oledb_parse_dt(oledb);
+ if (rc < 0) {
+ pr_err("Failed to parse common OLEDB device tree\n");
+ return rc;
+ }
+
+ rc = qpnp_oledb_hw_init(oledb);
+ if (rc < 0) {
+ pr_err("Failed to initialize OLEDB, rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = qpnp_oledb_register_regulator(oledb);
+ if (!rc)
+ pr_info("OLEDB registered successfully, ext_pin_en=%d mod_en=%d cuurent_voltage=%d mV\n",
+ oledb->ext_pin_control, oledb->mod_enable,
+ oledb->current_voltage);
+
+ return rc;
+}
+
+static int qpnp_oledb_regulator_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+const struct of_device_id qpnp_oledb_regulator_match_table[] = {
+ { .compatible = QPNP_OLEDB_REGULATOR_DRIVER_NAME,},
+ { },
+};
+
+static struct platform_driver qpnp_oledb_regulator_driver = {
+ .driver = {
+ .name = QPNP_OLEDB_REGULATOR_DRIVER_NAME,
+ .of_match_table = qpnp_oledb_regulator_match_table,
+ },
+ .probe = qpnp_oledb_regulator_probe,
+ .remove = qpnp_oledb_regulator_remove,
+};
+
+static int __init qpnp_oledb_regulator_init(void)
+{
+ return platform_driver_register(&qpnp_oledb_regulator_driver);
+}
+arch_initcall(qpnp_oledb_regulator_init);
+
+static void __exit qpnp_oledb_regulator_exit(void)
+{
+ platform_driver_unregister(&qpnp_oledb_regulator_driver);
+}
+module_exit(qpnp_oledb_regulator_exit);
+
+MODULE_DESCRIPTION("QPNP OLEDB driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("qpnp-oledb-regulator");