| commit | 8bc6d05b481aa7dc79c81b8ffac0da755e149643 | [log] [tgz] |
|---|---|---|
| author | David Daney <ddaney@caviumnetworks.com> | Mon Jan 05 15:29:58 2009 -0800 |
| committer | Ralf Baechle <ralf@linux-mips.org> | Fri Jan 30 21:32:58 2009 +0000 |
| tree | 0c6b7c62dbec9d598546c7e58cb13c0c78212a1e | |
| parent | 7adbedaf4469dcdcd6a1ab9bdeb8ad854d4f9827 [diff] |
MIPS: Read watch registers with interrupts disabled. If a context switch occurred between the watch exception and reading the watch registers, it would be possible for the new process to corrupt their state. Enabling interrupts only after the watch registers are read avoids this race. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>