tree 1f8d5cf4aa5599fb0b4e739279c29e9603a0fc3e
parent fb2a99e15ff0d342de4ba58c84a791224a96a01a
author Daniel Vetter <daniel.vetter@ffwll.ch> 1327700451 +0100
committer Dave Airlie <airlied@redhat.com> 1329134333 +0000

drm/modes: do not enforce an odd vtotal for interlaced modes

CEA actually specifies an interlaced mode with even vtotal and
supplies a diagram showing how this is supposed to work.

Note that interlaced modes with an even vtotal seem to be a fairly
recent invention. All modelines lore I could dig up with googling says
that vtotal for interlaced modes _needs_ to be odd. But the even
modelines in CEA are not a spec-bug, there's a figure in CEA-861-E
called "Figure 5 Special Interlaced Video Format Timing (Even Vtotal)"
that explains how it's supposed to work. Furthermore intel Bspec
explicitly mentions that both odd and even interlaced vtotal are
supported (VTOTAL register in the south display engine of PCH split
chips).

Acked-by: Adam Jackson <ajax@redhat.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Dave Airlie <airlied@redhat.com>