ARM: dts: msm: disable wcss and ssc cti on sdm670
Few of QDSS CTI's need some extra clock/regulator voted
to access them. WCSS and SSC subsystems on sdm670 cause
a kernel crash on access of CTI registers. Disable it.
Change-Id: Ic0d0c019ec68932fb3bec67d0b4c77e7794c050c
Signed-off-by: Saranya Chidura <schidura@codeaurora.org>
diff --git a/arch/arm64/boot/dts/qcom/sdm670-coresight.dtsi b/arch/arm64/boot/dts/qcom/sdm670-coresight.dtsi
index a885495..8323476 100644
--- a/arch/arm64/boot/dts/qcom/sdm670-coresight.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670-coresight.dtsi
@@ -1473,6 +1473,7 @@
reg-names = "cti-base";
coresight-name = "coresight-cti-wcss_cti0";
+ status = "disabled";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "apb_pclk";
@@ -1485,6 +1486,7 @@
reg-names = "cti-base";
coresight-name = "coresight-cti-wcss_cti1";
+ status = "disabled";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "apb_pclk";
@@ -1497,6 +1499,7 @@
reg-names = "cti-base";
coresight-name = "coresight-cti-wcss_cti2";
+ status = "disabled";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "apb_pclk";
@@ -1533,6 +1536,7 @@
reg-names = "cti-base";
coresight-name = "coresight-cti-ssc_sdc_cti2";
+ status = "disabled";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "apb_pclk";
@@ -1545,6 +1549,7 @@
reg-names = "cti-base";
coresight-name = "coresight-cti-ssc_cti1";
+ status = "disabled";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "apb_pclk";
@@ -1557,6 +1562,7 @@
reg-names = "cti-base";
coresight-name = "coresight-cti-ssc_q6_cti0";
+ status = "disabled";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "apb_pclk";
@@ -1569,6 +1575,7 @@
reg-names = "cti-base";
coresight-name = "coresight-cti-ssc_noc";
+ status = "disabled";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "apb_pclk";
@@ -1581,6 +1588,7 @@
reg-names = "cti-base";
coresight-name = "coresight-cti-ssc_noc_cti6";
+ status = "disabled";
clocks = <&clock_aop QDSS_CLK>;
clock-names = "apb_pclk";