tree bdb60e1592cc4af363774f07c1a2605dafa4bc89
parent ae6e694ef566ed69a2537c80771a9031ec627494
author Linus Walleij <linus.walleij@linaro.org> 1385133909 +0100
committer Linus Walleij <linus.walleij@linaro.org> 1388784474 +0100

clk: versatile: fixup IM-PD1 clock implementation

Register both VCO clocks, give per-logical module unique names
to the clocks so we can have several IM-PD1's connected (in
theory). Implement all the fixed-factor clocks as children of
VCO2.

Tested by using the UARTs and the PL181 MMC block on the IM-PD1,
works flawlessly.

Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>