| commit | 8e1c3aa30c2c3a5f982da9365a1ef03a3ac7a815 | [log] [tgz] |
|---|---|---|
| author | Geert Uytterhoeven <geert+renesas@glider.be> | Wed Sep 30 15:22:15 2015 +0200 |
| committer | Simon Horman <horms+renesas@verge.net.au> | Wed Feb 17 14:53:14 2016 +0900 |
| tree | 55f4980518428c6efe25f24bedb2d2cd9f88b1c5 | |
| parent | a528b4bf1a2ecb756aa65548fd5518fe82fb4648 [diff] |
arm64: dts: r8a7795: Add CA53 L2 cache-controller node Add a device node for the Cortex-A53 L2 cache-controller. The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>