| commit | 8ed5c0623272663783e052123fea02651464a0a5 | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <treding@nvidia.com> | Wed Apr 08 17:06:08 2015 +0200 |
| committer | Thierry Reding <treding@nvidia.com> | Thu Aug 13 13:47:16 2015 +0200 |
| tree | 54b8e1415d9187d5093a4669c7cf714553a1facc | |
| parent | 83a3c223cc5678c5ced554fa2819747fd53437c7 [diff] |
gpu: host1x: mipi: Fix clock lane register for DSI Use more consistent names for the clock lane configuration registers and fix the offset of the upper clock lane configuration register for the first DSI pad. Signed-off-by: Thierry Reding <treding@nvidia.com>