| commit | 8f0767611a0ed719caf975d899d8431834ace2d8 | [log] [tgz] |
|---|---|---|
| author | Andrea Venturi <ennesimamail.av@gmail.com> | Mon Mar 21 17:10:38 2016 +0100 |
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | Fri Apr 22 00:29:21 2016 +0200 |
| tree | 5c5bf867e6b491b5c2e408ab8c9191461e96c68c | |
| parent | 92a39d9043ba5ff98adb1c31491f00c7bea5466e [diff] |
clk: sunxi: mod1 clock should modify it's parent add CLK_SET_RATE_PARENT to modify the rate on clk upstream Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>