| commit | 8fff6e389c2c7366eafc9985d83e61d46528ca83 | [log] [tgz] |
|---|---|---|
| author | Casey Piper <cpiper@codeaurora.org> | Mon Aug 03 15:07:10 2015 -0700 |
| committer | Narendra Muppalla <NarendraM@codeaurora.org> | Wed Jan 18 18:14:35 2017 -0800 |
| tree | 506b05f649cc6ef81ca49a9f47bee666c40b5c9d | |
| parent | 1b3a62002a7971fac9dd6c4c329733bf8bc45510 [diff] |
clk: msm: hdmi: Increase PLL ready bit timeout When using 4k resolutions at 60fps, the PLL ready bit will take slightly longer than other video modes. Increase the timeout value to ensure that the PLL lock is successful. Also modify the lane mode values to improve Shmoo margin with low core voltage. Change-Id: I9d65535b941e755fe706e4dd61cb357a7a62cdc2 Signed-off-by: Casey Piper <cpiper@codeaurora.org>