tree 506b05f649cc6ef81ca49a9f47bee666c40b5c9d
parent 1b3a62002a7971fac9dd6c4c329733bf8bc45510
author Casey Piper <cpiper@codeaurora.org> 1438639630 -0700
committer Narendra Muppalla <NarendraM@codeaurora.org> 1484792075 -0800

clk: msm: hdmi: Increase PLL ready bit timeout

When using 4k resolutions at 60fps, the PLL
ready bit will take slightly longer than other
video modes. Increase the timeout value to
ensure that the PLL lock is successful. Also
modify the lane mode values to improve Shmoo
margin with low core voltage.

Change-Id: I9d65535b941e755fe706e4dd61cb357a7a62cdc2
Signed-off-by: Casey Piper <cpiper@codeaurora.org>