| commit | 903bfeac50ecc7725db606c19edbbc93966772c2 | [log] [tgz] |
|---|---|---|
| author | Andy Walls <awalls@radix.net> | Thu Jan 01 11:09:24 2009 -0300 |
| committer | Mauro Carvalho Chehab <mchehab@redhat.com> | Mon Mar 30 12:42:24 2009 -0300 |
| tree | 71723b6a3c6444a1720c03df614bc443df36ba95 | |
| parent | f97d2074e364d51dde91d2a94a262466815d13ce [diff] |
V4L/DVB (10274): cx18: Fix a PLL divisor update for the I2S master clock A redundant PLL divisior update for the I2S master clock after AV core firmware load was missed in earlier PLL parameter changes. This one really doesn't matter because it's redundant and gets overwritten, but the driver should be self consistent in the values used. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>