| commit | 9062511097683b4422f023d181b4a8b2db1a7a72 | [log] [tgz] |
|---|---|---|
| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | Sun Jan 23 22:51:09 2011 +0530 |
| committer | Kevin Hilman <khilman@ti.com> | Thu Mar 10 12:23:13 2011 -0800 |
| tree | 9e46fb8c0491a26bb25464d90b6cd4caf92edf5b | |
| parent | 46f557cb453b9f3b6dc36b8179c2c36932a2ea64 [diff] |
OMAP3: PM: Clear the SCTLR C bit in asm code to prevent data cache allocation On the newer ARM processors like CortexA8, CortexA9, the caches can be speculatively loaded while they are getting flushed. Clear the SCTLR C bit to prevent further data cache allocation as part of cache clean routine Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>