clk: msm: Add delay of 50uSec before polling lock_detect status
Some PLL HWs require an additional delay for the PLL lock detect
to stabilize after being brought out of reset and SW to poll for
lock detect status. Add delay of 50uSec before polling lock_det
bit by introducing new pll ops.
Also if PLL fails to lock, record additional PLL debug information
in the kernel log before panic().
Change-Id: I1b04dccc8d3c3e45d4aa7a3c1c60311331e490fa
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
2 files changed