diff --git a/drivers/staging/brcm80211/util/aiutils.c b/drivers/staging/brcm80211/util/aiutils.c
index 43bb852a..6ac49ec 100644
--- a/drivers/staging/brcm80211/util/aiutils.c
+++ b/drivers/staging/brcm80211/util/aiutils.c
@@ -319,7 +319,7 @@
 	void *regs;
 
 	if (coreidx >= sii->numcores)
-		return (NULL);
+		return NULL;
 
 	/*
 	 * If the user has provided an interrupt mask enabled function,
@@ -427,7 +427,7 @@
 	}
 	ai = sii->curwrap;
 
-	return (R_REG(sii->osh, &ai->oobselouta30) & 0x1f);
+	return R_REG(sii->osh, &ai->oobselouta30) & 0x1f;
 }
 
 void ai_setint(si_t *sih, int siflag)
@@ -449,7 +449,7 @@
 
 	sii = SI_INFO(sih);
 	cia = sii->cia[sii->curidx];
-	return ((cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT);
+	return (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
 }
 
 uint ai_corerev(si_t *sih)
@@ -459,7 +459,7 @@
 
 	sii = SI_INFO(sih);
 	cib = sii->cib[sii->curidx];
-	return ((cib & CIB_REV_MASK) >> CIB_REV_SHIFT);
+	return (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
 }
 
 bool ai_iscoreup(si_t *sih)
@@ -568,7 +568,7 @@
 		INTR_RESTORE(sii, intr_val);
 	}
 
-	return (w);
+	return w;
 }
 
 void ai_core_disable(si_t *sih, uint32 bits)
diff --git a/drivers/staging/brcm80211/util/bcmotp.c b/drivers/staging/brcm80211/util/bcmotp.c
index f76e64e..9011ed9 100644
--- a/drivers/staging/brcm80211/util/bcmotp.c
+++ b/drivers/staging/brcm80211/util/bcmotp.c
@@ -553,13 +553,13 @@
 static int hndotp_status(void *oh)
 {
 	otpinfo_t *oi = (otpinfo_t *) oh;
-	return ((int)(oi->hwprot | oi->signvalid));
+	return (int)(oi->hwprot | oi->signvalid);
 }
 
 static int hndotp_size(void *oh)
 {
 	otpinfo_t *oi = (otpinfo_t *) oh;
-	return ((int)(oi->size));
+	return (int)(oi->size);
 }
 
 static uint16 hndotp_otpr(void *oh, chipcregs_t *cc, uint wn)
@@ -574,7 +574,7 @@
 	osh = si_osh(oi->sih);
 
 	ptr = (volatile uint16 *)((volatile char *)cc + CC_SROM_OTP);
-	return (R_REG(osh, &ptr[wn]));
+	return R_REG(osh, &ptr[wn]);
 }
 
 static uint16 hndotp_otproff(void *oh, chipcregs_t *cc, int woff)
@@ -591,7 +591,7 @@
 
 	ptr = (volatile uint16 *)((volatile char *)cc + CC_SROM_OTP);
 
-	return (R_REG(osh, &ptr[(oi->size / 2) + woff]));
+	return R_REG(osh, &ptr[(oi->size / 2) + woff]);
 }
 
 static uint16 hndotp_read_bit(void *oh, chipcregs_t *cc, uint idx)
diff --git a/drivers/staging/brcm80211/util/bcmsrom.c b/drivers/staging/brcm80211/util/bcmsrom.c
index f922a5c..cb412f8 100644
--- a/drivers/staging/brcm80211/util/bcmsrom.c
+++ b/drivers/staging/brcm80211/util/bcmsrom.c
@@ -161,7 +161,7 @@
 
 	ASSERT(bustype == BUSTYPE(bustype));
 	if (vars == NULL || count == NULL)
-		return (0);
+		return 0;
 
 	*vars = NULL;
 	*count = 0;
@@ -174,7 +174,7 @@
 	case PCI_BUS:
 		ASSERT(curmap != NULL);
 		if (curmap == NULL)
-			return (-1);
+			return -1;
 
 		return initvars_srom_pci(sih, curmap, vars, count);
 
@@ -186,7 +186,7 @@
 	default:
 		ASSERT(0);
 	}
-	return (-1);
+	return -1;
 }
 
 /* support only 16-bit word read from srom */
@@ -2027,7 +2027,7 @@
 	while (fn-- > 0)
 		MFREE(osh, cis[fn], SBSDIO_CIS_SIZE_LIMIT);
 
-	return (rc);
+	return rc;
 }
 
 /* set SDIO sprom command register */
diff --git a/drivers/staging/brcm80211/util/bcmutils.c b/drivers/staging/brcm80211/util/bcmutils.c
index 73f3bb8..28483d5 100644
--- a/drivers/staging/brcm80211/util/bcmutils.c
+++ b/drivers/staging/brcm80211/util/bcmutils.c
@@ -100,7 +100,7 @@
 	total = 0;
 	for (; p; p = PKTNEXT(p))
 		total += PKTLEN(p);
-	return (total);
+	return total;
 }
 
 /* return the last buffer of chained pkt */
@@ -108,7 +108,7 @@
 {
 	for (; PKTNEXT(p); p = PKTNEXT(p)) ;
 
-	return (p);
+	return p;
 }
 
 /* count segments of a chained packet */
@@ -399,7 +399,7 @@
 	if (prec_out)
 		*prec_out = prec;
 
-	return (pq->q[prec].head);
+	return pq->q[prec].head;
 }
 
 void *pktq_peek_tail(struct pktq *pq, int *prec_out)
@@ -416,7 +416,7 @@
 	if (prec_out)
 		*prec_out = prec;
 
-	return (pq->q[prec].tail);
+	return pq->q[prec].tail;
 }
 
 void pktq_flush(osl_t *osh, struct pktq *pq, bool dir, ifpkt_cb_t fn, int arg)
@@ -578,7 +578,7 @@
 	if (endp)
 		*endp = (char *)cp;
 
-	return (result);
+	return result;
 }
 
 int BCMROMFN(bcm_atoi) (char *s)
@@ -593,15 +593,15 @@
 	int i;
 
 	if ((haystack == NULL) || (needle == NULL))
-		return (haystack);
+		return haystack;
 
 	nlen = strlen(needle);
 	len = strlen(haystack) - nlen + 1;
 
 	for (i = 0; i < len; i++)
 		if (memcmp(needle, &haystack[i], nlen) == 0)
-			return (&haystack[i]);
-	return (NULL);
+			return &haystack[i];
+	return NULL;
 }
 
 char *BCMROMFN(bcmstrcat) (char *dest, const char *src)
@@ -612,7 +612,7 @@
 
 	while ((*p++ = *src++) != '\0') ;
 
-	return (dest);
+	return dest;
 }
 
 char *BCMROMFN(bcmstrncat) (char *dest, const char *src, uint size)
@@ -625,7 +625,7 @@
 
 	while (p != endp && (*p++ = *src++) != '\0') ;
 
-	return (dest);
+	return dest;
 }
 
 /****************************************************************************
@@ -793,13 +793,13 @@
 			break;
 	}
 
-	return (i == 6);
+	return i == 6;
 }
 
 char *bcm_ether_ntoa(const struct ether_addr *ea, char *buf)
 {
 	snprintf(buf, 18, "%pM", ea->octet);
-	return (buf);
+	return buf;
 }
 
 void bcm_mdelay(uint ms)
@@ -830,13 +830,13 @@
 	/* first look in vars[] */
 	for (s = vars; s && *s;) {
 		if ((bcmp(s, name, len) == 0) && (s[len] == '='))
-			return (&s[len + 1]);
+			return &s[len + 1];
 
 		while (*s++) ;
 	}
 
 	/* then query nvram */
-	return (nvram_get(name));
+	return nvram_get(name);
 }
 
 /*
@@ -848,9 +848,9 @@
 	char *val;
 
 	if ((val = getvar(vars, name)) == NULL)
-		return (0);
+		return 0;
 
-	return (bcm_strtoul(val, NULL, 0));
+	return bcm_strtoul(val, NULL, 0);
 }
 
 int getintvararray(char *vars, const char *name, uint8 index)
@@ -860,7 +860,7 @@
 	int val = 0;
 
 	if ((buf = getvar(vars, name)) == NULL) {
-		return (0);
+		return 0;
 	}
 
 	/* table values are always separated by "," or " " */
@@ -891,7 +891,7 @@
 		string = c + 1;
 	}
 
-	return (!strcmp(string, name));
+	return !strcmp(string, name);
 }
 
 /* Return gpio pin number assigned to the named pin
@@ -1301,7 +1301,7 @@
 
 		/* validate remaining totlen */
 		if ((elt->id == key) && (totlen >= (len + 2)))
-			return (elt);
+			return elt;
 
 		elt = (bcm_tlv_t *) ((uint8 *) elt + (len + 2));
 		totlen -= (len + 2);
@@ -1331,11 +1331,11 @@
 
 		/* Punt if we start seeing IDs > than target key */
 		if (id > key)
-			return (NULL);
+			return NULL;
 
 		/* validate remaining totlen */
 		if ((id == key) && (totlen >= (len + 2)))
-			return (elt);
+			return elt;
 
 		elt = (bcm_tlv_t *) ((uint8 *) elt + (len + 2));
 		totlen -= (len + 2);
@@ -1496,7 +1496,7 @@
 		snprintf(buf, 8, "%c%03x",
 			 ((brev & 0xf000) == 0x1000) ? 'P' : 'A', brev & 0xfff);
 
-	return (buf);
+	return buf;
 }
 
 #define BUFSIZE_TODUMP_ATONCE 512	/* Buffer size */
@@ -1621,7 +1621,7 @@
 	/* return the mW value scaled down to the correct factor of 10,
 	 * adding in factor/2 to get proper rounding.
 	 */
-	return ((nqdBm_to_mW_map[idx] + factor / 2) / factor);
+	return (nqdBm_to_mW_map[idx] + factor / 2) / factor;
 }
 
 uint8 BCMROMFN(bcm_mw_to_qdbm) (uint16 mw)
@@ -1652,7 +1652,7 @@
 
 	qdbm += (uint8) offset;
 
-	return (qdbm);
+	return qdbm;
 }
 
 uint BCMROMFN(bcm_bitcount) (uint8 *bitmap, uint length)
@@ -1719,7 +1719,7 @@
 
 	for (i = nbytes - 1; i >= 0; i--) {
 		if (arg1[i] != arg2[i])
-			return (arg1[i] - arg2[i]);
+			return arg1[i] - arg2[i];
 	}
 	return 0;
 }
diff --git a/drivers/staging/brcm80211/util/bcmwifi.c b/drivers/staging/brcm80211/util/bcmwifi.c
index ae5ff88..5eced8e 100644
--- a/drivers/staging/brcm80211/util/bcmwifi.c
+++ b/drivers/staging/brcm80211/util/bcmwifi.c
@@ -79,7 +79,7 @@
 
 	/* Outputs a max of 6 chars including '\0'  */
 	snprintf(buf, 6, "%d%s%s%s", channel, band, bw, sb);
-	return (buf);
+	return buf;
 }
 
 /* given a chanspec string, convert to a chanspec.
@@ -145,7 +145,7 @@
 	}
 
  done:
-	return (channel | band | bw | ctl_sb);
+	return channel | band | bw | ctl_sb;
 }
 
 /*
diff --git a/drivers/staging/brcm80211/util/hnddma.c b/drivers/staging/brcm80211/util/hnddma.c
index 4b642d6..9c5f58a 100644
--- a/drivers/staging/brcm80211/util/hnddma.c
+++ b/drivers/staging/brcm80211/util/hnddma.c
@@ -368,7 +368,7 @@
 		printf("dma_attach: out of memory, malloced %d bytes\n",
 		       MALLOCED(osh));
 #endif
-		return (NULL);
+		return NULL;
 	}
 
 	bzero((char *)di, sizeof(dma_info_t));
@@ -560,11 +560,11 @@
 		}
 	}
 
-	return ((hnddma_t *) di);
+	return (hnddma_t *) di;
 
  fail:
 	_dma_detach(di);
-	return (NULL);
+	return NULL;
 }
 
 /* init the tx or rx descriptor */
@@ -602,7 +602,7 @@
 	data ^= data >> 2;
 	data ^= data >> 1;
 
-	return (data & 1);
+	return data & 1;
 }
 
 #define DMA64_DD_PARITY(dd)  parity32((dd)->addrlow ^ (dd)->addrhigh ^ (dd)->ctrl1 ^ (dd)->ctrl2)
@@ -660,7 +660,7 @@
 	OR_REG(osh, &dma32regs->control, XC_AE);
 	w = R_REG(osh, &dma32regs->control);
 	AND_REG(osh, &dma32regs->control, ~XC_AE);
-	return ((w & XC_AE) == XC_AE);
+	return (w & XC_AE) == XC_AE;
 }
 
 static bool _dma_alloc(dma_info_t *di, uint direction)
@@ -774,9 +774,9 @@
 		return FALSE;
 	} else if (DMA32_ENAB(di)) {
 		if (di->d32txregs)
-			return (_dma32_addrext(di->osh, di->d32txregs));
+			return _dma32_addrext(di->osh, di->d32txregs);
 		else if (di->d32rxregs)
-			return (_dma32_addrext(di->osh, di->d32rxregs));
+			return _dma32_addrext(di->osh, di->d32rxregs);
 	} else
 		ASSERT(0);
 
@@ -978,7 +978,7 @@
  next_frame:
 	head = _dma_getnextrxp(di, FALSE);
 	if (head == NULL)
-		return (NULL);
+		return NULL;
 
 	len = ltoh16(*(uint16 *) (PKTDATA(head)));
 	DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
@@ -1035,7 +1035,7 @@
 		}
 	}
 
-	return (head);
+	return head;
 }
 
 /* post receive buffers
@@ -1160,7 +1160,7 @@
 	uint end, i;
 
 	if (di->ntxd == 0)
-		return (NULL);
+		return NULL;
 
 	if (DMA64_ENAB(di) && DMA64_MODE(di)) {
 		end =
@@ -1176,9 +1176,9 @@
 
 	for (i = di->txin; i != end; i = NEXTTXD(i))
 		if (di->txp[i])
-			return (di->txp[i]);
+			return di->txp[i];
 
-	return (NULL);
+	return NULL;
 }
 
 /* like getnextrxp but not take off the ring */
@@ -1187,7 +1187,7 @@
 	uint end, i;
 
 	if (di->nrxd == 0)
-		return (NULL);
+		return NULL;
 
 	if (DMA64_ENAB(di) && DMA64_MODE(di)) {
 		end =
@@ -1203,9 +1203,9 @@
 
 	for (i = di->rxin; i != end; i = NEXTRXD(i))
 		if (di->rxp[i])
-			return (di->rxp[i]);
+			return di->rxp[i];
 
-	return (NULL);
+	return NULL;
 }
 
 static void _dma_rxreclaim(dma_info_t *di)
@@ -1226,7 +1226,7 @@
 static void *BCMFASTPATH _dma_getnextrxp(dma_info_t *di, bool forceall)
 {
 	if (di->nrxd == 0)
-		return (NULL);
+		return NULL;
 
 	if (DMA64_ENAB(di) && DMA64_MODE(di)) {
 		return dma64_getnextrxp(di, forceall);
@@ -1307,7 +1307,7 @@
 
 	if (di == NULL) {
 		DMA_ERROR(("%s: _dma_ctrlflags: NULL dma handle\n", di->name));
-		return (0);
+		return 0;
 	}
 
 	ASSERT((flags & ~mask) == 0);
@@ -1350,18 +1350,18 @@
 
 	di->hnddma.dmactrlflags = dmactrlflags;
 
-	return (dmactrlflags);
+	return dmactrlflags;
 }
 
 /* get the address of the var in order to change later */
 static uintptr _dma_getvar(dma_info_t *di, const char *name)
 {
 	if (!strcmp(name, "&txavail"))
-		return ((uintptr) & (di->hnddma.txavail));
+		return (uintptr) & (di->hnddma.txavail);
 	else {
 		ASSERT(0);
 	}
-	return (0);
+	return 0;
 }
 
 void dma_txpioloopback(osl_t *osh, dma32regs_t *regs)
@@ -1378,7 +1378,7 @@
 	while (size >>= 1) {
 		bitpos++;
 	}
-	return (bitpos);
+	return bitpos;
 }
 
 /* This function ensures that the DMA descriptor ring will not get allocated
@@ -1441,7 +1441,7 @@
 
 	/* If the chip is dead, it is not enabled :-) */
 	xc = R_REG(di->osh, &di->d32txregs->control);
-	return ((xc != 0xffffffff) && (xc & XC_XE));
+	return (xc != 0xffffffff) && (xc & XC_XE);
 }
 
 static void dma32_txsuspend(dma_info_t *di)
@@ -1586,7 +1586,7 @@
 	/* wait for the last transaction to complete */
 	OSL_DELAY(300);
 
-	return (status == XS_XS_DISABLED);
+	return status == XS_XS_DISABLED;
 }
 
 static bool dma32_rxidle(dma_info_t *di)
@@ -1612,7 +1612,7 @@
 				   &di->d32rxregs->status) & RS_RS_MASK)) !=
 		  RS_RS_DISABLED), 10000);
 
-	return (status == RS_RS_DISABLED);
+	return status == RS_RS_DISABLED;
 }
 
 static bool dma32_rxenabled(dma_info_t *di)
@@ -1620,7 +1620,7 @@
 	uint32 rc;
 
 	rc = R_REG(di->osh, &di->d32rxregs->control);
-	return ((rc != 0xffffffff) && (rc & RC_RE));
+	return (rc != 0xffffffff) && (rc & RC_RE);
 }
 
 static bool dma32_txsuspendedidle(dma_info_t *di)
@@ -1752,14 +1752,14 @@
 	/* tx flow control */
 	di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
 
-	return (0);
+	return 0;
 
  outoftxd:
 	DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
 	PKTFREE(di->osh, p0, TRUE);
 	di->hnddma.txavail = 0;
 	di->hnddma.txnobuf++;
-	return (-1);
+	return -1;
 }
 
 /*
@@ -1785,7 +1785,7 @@
 		    "transfered")));
 
 	if (di->ntxd == 0)
-		return (NULL);
+		return NULL;
 
 	txp = NULL;
 
@@ -1850,11 +1850,11 @@
 	/* tx flow control */
 	di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
 
-	return (txp);
+	return txp;
 
  bogus:
 	DMA_NONE(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n", start, end, di->txout, forceall));
-	return (NULL);
+	return NULL;
 }
 
 static void *dma32_getnextrxp(dma_info_t *di, bool forceall)
@@ -1869,14 +1869,14 @@
 
 	/* return if no packets posted */
 	if (i == di->rxout)
-		return (NULL);
+		return NULL;
 
 	curr =
 	    B2I(R_REG(di->osh, &di->d32rxregs->status) & RS_CD_MASK, dma32dd_t);
 
 	/* ignore curr if forceall */
 	if (!forceall && (i == curr))
-		return (NULL);
+		return NULL;
 
 	/* get the packet pointer that corresponds to the rx descriptor */
 	rxp = di->rxp[i];
@@ -1895,7 +1895,7 @@
 
 	di->rxin = NEXTRXD(i);
 
-	return (rxp);
+	return rxp;
 }
 
 /*
@@ -2009,7 +2009,7 @@
 
 	/* If the chip is dead, it is not enabled :-) */
 	xc = R_REG(di->osh, &di->d64txregs->control);
-	return ((xc != 0xffffffff) && (xc & D64_XC_XE));
+	return (xc != 0xffffffff) && (xc & D64_XC_XE);
 }
 
 static void dma64_txsuspend(dma_info_t *di)
@@ -2153,7 +2153,7 @@
 	/* wait for the last transaction to complete */
 	OSL_DELAY(300);
 
-	return (status == D64_XS0_XS_DISABLED);
+	return status == D64_XS0_XS_DISABLED;
 }
 
 static bool dma64_rxidle(dma_info_t *di)
@@ -2179,7 +2179,7 @@
 		   (R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_RS_MASK))
 		  != D64_RS0_RS_DISABLED), 10000);
 
-	return (status == D64_RS0_RS_DISABLED);
+	return status == D64_RS0_RS_DISABLED;
 }
 
 static bool dma64_rxenabled(dma_info_t *di)
@@ -2187,7 +2187,7 @@
 	uint32 rc;
 
 	rc = R_REG(di->osh, &di->d64rxregs->control);
-	return ((rc != 0xffffffff) && (rc & D64_RC_RE));
+	return (rc != 0xffffffff) && (rc & D64_RC_RE);
 }
 
 static bool dma64_txsuspendedidle(dma_info_t *di)
@@ -2286,13 +2286,13 @@
 	/* tx flow control */
 	di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
 
-	return (0);
+	return 0;
 
  outoftxd:
 	DMA_ERROR(("%s: %s: out of txds !!!\n", di->name, __func__));
 	di->hnddma.txavail = 0;
 	di->hnddma.txnobuf++;
-	return (-1);
+	return -1;
 }
 
 /* !! tx entry routine
@@ -2404,14 +2404,14 @@
 	/* tx flow control */
 	di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
 
-	return (0);
+	return 0;
 
  outoftxd:
 	DMA_ERROR(("%s: dma_txfast: out of txds !!!\n", di->name));
 	PKTFREE(di->osh, p0, TRUE);
 	di->hnddma.txavail = 0;
 	di->hnddma.txnobuf++;
-	return (-1);
+	return -1;
 }
 
 /*
@@ -2437,7 +2437,7 @@
 		    "transfered")));
 
 	if (di->ntxd == 0)
-		return (NULL);
+		return NULL;
 
 	txp = NULL;
 
@@ -2509,11 +2509,11 @@
 	/* tx flow control */
 	di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
 
-	return (txp);
+	return txp;
 
  bogus:
 	DMA_NONE(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n", start, end, di->txout, forceall));
-	return (NULL);
+	return NULL;
 }
 
 static void *BCMFASTPATH dma64_getnextrxp(dma_info_t *di, bool forceall)
@@ -2529,7 +2529,7 @@
 
 	/* return if no packets posted */
 	if (i == di->rxout)
-		return (NULL);
+		return NULL;
 
 	curr =
 	    B2I(((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_CD_MASK) -
@@ -2537,7 +2537,7 @@
 
 	/* ignore curr if forceall */
 	if (!forceall && (i == curr))
-		return (NULL);
+		return NULL;
 
 	/* get the packet pointer that corresponds to the rx descriptor */
 	rxp = di->rxp[i];
@@ -2559,7 +2559,7 @@
 
 	di->rxin = NEXTRXD(i);
 
-	return (rxp);
+	return rxp;
 }
 
 static bool _dma64_addrext(osl_t *osh, dma64regs_t * dma64regs)
@@ -2568,7 +2568,7 @@
 	OR_REG(osh, &dma64regs->control, D64_XC_AE);
 	w = R_REG(osh, &dma64regs->control);
 	AND_REG(osh, &dma64regs->control, ~D64_XC_AE);
-	return ((w & D64_XC_AE) == D64_XC_AE);
+	return (w & D64_XC_AE) == D64_XC_AE;
 }
 
 /*
@@ -2666,12 +2666,12 @@
 			if ((BUSTYPE(sih->bustype) == SI_BUS) ||
 			    ((BUSTYPE(sih->bustype) == PCI_BUS) &&
 			     (sih->buscoretype == PCIE_CORE_ID)))
-				return (DMADDRWIDTH_64);
+				return DMADDRWIDTH_64;
 
 		/* DMA64 is always 32-bit capable, AE is always TRUE */
 		ASSERT(_dma64_addrext(osh, (dma64regs_t *) dmaregs));
 
-		return (DMADDRWIDTH_32);
+		return DMADDRWIDTH_32;
 	}
 
 	/* Start checking for 32-bit / 30-bit addressing */
@@ -2682,8 +2682,8 @@
 	    ((BUSTYPE(sih->bustype) == PCI_BUS)
 	     && sih->buscoretype == PCIE_CORE_ID)
 	    || (_dma32_addrext(osh, dma32regs)))
-		return (DMADDRWIDTH_32);
+		return DMADDRWIDTH_32;
 
 	/* Fallthru */
-	return (DMADDRWIDTH_30);
+	return DMADDRWIDTH_30;
 }
diff --git a/drivers/staging/brcm80211/util/hndpmu.c b/drivers/staging/brcm80211/util/hndpmu.c
index 9ec07e7..3781696 100644
--- a/drivers/staging/brcm80211/util/hndpmu.c
+++ b/drivers/staging/brcm80211/util/hndpmu.c
@@ -589,7 +589,7 @@
 static bool BCMATTACHFN(si_pmu_res_depfltr_ncb) (si_t *sih)
 {
 
-	return ((sih->boardflags & BFL_NOCBUCK) != 0);
+	return (sih->boardflags & BFL_NOCBUCK) != 0;
 }
 
 /* TRUE if the power topology uses the PALDO */
@@ -1656,7 +1656,7 @@
 	if (CHIPID(sih->chip) == BCM5357_CHIP_ID) {
 		/* Detect failure in clock setting */
 		if ((R_REG(osh, &cc->chipstatus) & 0x40000) != 0) {
-			return (133 * 1000000);
+			return 133 * 1000000;
 		}
 	}
 
@@ -1684,7 +1684,7 @@
 		  __func__, p1, p2, ndiv, ndiv, m, div, fc, fc / div));
 
 	/* Return clock in Hertz */
-	return ((fc / div) * 1000000);
+	return (fc / div) * 1000000;
 }
 
 /* query backplane clock frequency */
@@ -2617,7 +2617,7 @@
 	/* Return to original core */
 	si_setcoreidx(sih, origidx);
 
-	return (R_REG(osh, &cc->pmustatus) & clk);
+	return R_REG(osh, &cc->pmustatus) & clk;
 }
 
 /*
diff --git a/drivers/staging/brcm80211/util/linux_osl.c b/drivers/staging/brcm80211/util/linux_osl.c
index 725f90d..694a5df 100644
--- a/drivers/staging/brcm80211/util/linux_osl.c
+++ b/drivers/staging/brcm80211/util/linux_osl.c
@@ -187,7 +187,7 @@
 		osh->pub.pktalloced++;
 	}
 
-	return ((void *)skb);
+	return (void *)skb;
 }
 
 /* Free the driver packet. Free the tag if present */
@@ -246,7 +246,7 @@
 		       offset, (PCI_CFG_RETRY - retry));
 #endif				/* BCMDBG */
 
-	return (val);
+	return val;
 }
 
 void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
@@ -315,12 +315,12 @@
 	if ((addr = kmalloc(size, GFP_ATOMIC)) == NULL) {
 		if (osh)
 			osh->failed++;
-		return (NULL);
+		return NULL;
 	}
 	if (osh)
 		osh->malloced += size;
 
-	return (addr);
+	return addr;
 }
 
 void osl_mfree(osl_t *osh, void *addr, uint size)
@@ -335,18 +335,18 @@
 uint osl_malloced(osl_t *osh)
 {
 	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
-	return (osh->malloced);
+	return osh->malloced;
 }
 
 uint osl_malloc_failed(osl_t *osh)
 {
 	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
-	return (osh->failed);
+	return osh->failed;
 }
 
 uint osl_dma_consistent_align(void)
 {
-	return (PAGE_SIZE);
+	return PAGE_SIZE;
 }
 
 void *osl_dma_alloc_consistent(osl_t *osh, uint size, uint16 align_bits,
@@ -359,7 +359,7 @@
 		size += align;
 	*alloced = size;
 
-	return (pci_alloc_consistent(osh->pdev, size, (dma_addr_t *) pap));
+	return pci_alloc_consistent(osh->pdev, size, (dma_addr_t *) pap);
 }
 
 void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa)
@@ -375,7 +375,7 @@
 
 	ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
 	dir = (direction == DMA_TX) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE;
-	return (pci_map_single(osh->pdev, va, size, dir));
+	return pci_map_single(osh->pdev, va, size, dir);
 }
 
 void BCMFASTPATH osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction)
@@ -461,7 +461,7 @@
 
 	/* Increment the packet counter */
 	osh->pub.pktalloced++;
-	return (p);
+	return p;
 }
 
 #ifdef BCMSDIO
diff --git a/drivers/staging/brcm80211/util/nicpci.c b/drivers/staging/brcm80211/util/nicpci.c
index 67dcd21..76105a0 100644
--- a/drivers/staging/brcm80211/util/nicpci.c
+++ b/drivers/staging/brcm80211/util/nicpci.c
@@ -116,7 +116,7 @@
 	if ((pi = MALLOC(osh, sizeof(pcicore_info_t))) == NULL) {
 		PCI_ERROR(("pci_attach: malloc failed! malloced %d bytes\n",
 			   MALLOCED(osh)));
-		return (NULL);
+		return NULL;
 	}
 
 	bzero(pi, sizeof(pcicore_info_t));
@@ -733,7 +733,7 @@
 
 	pmecap = OSL_PCI_READ_CONFIG(osh, cap_ptr, sizeof(uint32));
 
-	return ((pmecap & PME_CAP_PM_STATES) != 0);
+	return (pmecap & PME_CAP_PM_STATES) != 0;
 }
 
 /* return TRUE if PM capability exists in the pci config space
@@ -762,7 +762,7 @@
 		pi->pmecap = (pmecap & PME_CAP_PM_STATES) != 0;
 	}
 
-	return (pi->pmecap);
+	return pi->pmecap;
 }
 
 /* Enable PME generation */
diff --git a/drivers/staging/brcm80211/util/nvram/nvram_ro.c b/drivers/staging/brcm80211/util/nvram/nvram_ro.c
index 941fed3..06fe278 100644
--- a/drivers/staging/brcm80211/util/nvram/nvram_ro.c
+++ b/drivers/staging/brcm80211/util/nvram/nvram_ro.c
@@ -131,7 +131,7 @@
 
 	for (s = vars; (s < lim) && *s;) {
 		if ((bcmp(s, name, len) == 0) && (s[len] == '='))
-			return (&s[len + 1]);
+			return &s[len + 1];
 
 		while (*s++) ;
 	}
diff --git a/drivers/staging/brcm80211/util/qmath.c b/drivers/staging/brcm80211/util/qmath.c
index 17844b3..dc6e715 100644
--- a/drivers/staging/brcm80211/util/qmath.c
+++ b/drivers/staging/brcm80211/util/qmath.c
@@ -43,7 +43,7 @@
 */
 int32 qm_mul321616(int16 op1, int16 op2)
 {
-	return ((int32) (op1) * (int32) (op2));
+	return (int32) (op1) * (int32) (op2);
 }
 
 /*
@@ -55,7 +55,7 @@
 {
 	int32 result;
 	result = ((int32) (op1) * (int32) (op2));
-	return ((int16) (result >> 16));
+	return (int16) (result >> 16);
 }
 
 /*
@@ -101,7 +101,7 @@
 	} else {
 		result = ((int32) (op1) * (int32) (op2));
 	}
-	return ((int16) (result >> 15));
+	return (int16) (result >> 15);
 }
 
 /*
@@ -311,7 +311,7 @@
 		}
 	}
 	var_out = (int16) (L_num & 0x7fff);
-	return (var_out);
+	return var_out;
 }
 
 /*
diff --git a/drivers/staging/brcm80211/util/siutils.c b/drivers/staging/brcm80211/util/siutils.c
index 0053707..d9a64eb 100644
--- a/drivers/staging/brcm80211/util/siutils.c
+++ b/drivers/staging/brcm80211/util/siutils.c
@@ -91,13 +91,13 @@
 	if ((sii = MALLOC(osh, sizeof(si_info_t))) == NULL) {
 		SI_ERROR(("si_attach: malloc failed! malloced %d bytes\n",
 			  MALLOCED(osh)));
-		return (NULL);
+		return NULL;
 	}
 
 	if (si_doattach(sii, devid, osh, regs, bustype, sdh, vars, varsz) ==
 	    NULL) {
 		MFREE(osh, sii, sizeof(si_info_t));
-		return (NULL);
+		return NULL;
 	}
 	sii->vars = vars ? *vars : NULL;
 	sii->varsz = varsz ? *varsz : 0;
@@ -465,7 +465,7 @@
 	sb_taclear(sih, FALSE);
 #endif				/* BCMDBG */
 
-	return (sii);
+	return sii;
 
  exit:
 	return NULL;
@@ -654,7 +654,7 @@
 		si_chipcontrl_epa4331(sih, TRUE);
 	}
 
-	return (sii);
+	return sii;
  exit:
 	if (BUSTYPE(sih->bustype) == PCI_BUS) {
 		if (sii->pch)
@@ -818,7 +818,7 @@
 		if (sii->coreid[i] == coreid)
 			coreunit++;
 
-	return (coreunit);
+	return coreunit;
 }
 
 uint si_corevendor(si_t *sih)
@@ -833,7 +833,7 @@
 
 bool si_backplane64(si_t *sih)
 {
-	return ((sih->cccaps & CC_CAP_BKPLN64) != 0);
+	return (sih->cccaps & CC_CAP_BKPLN64) != 0;
 }
 
 #ifndef BCMSDIO
@@ -862,11 +862,11 @@
 	for (i = 0; i < sii->numcores; i++)
 		if (sii->coreid[i] == coreid) {
 			if (found == coreunit)
-				return (i);
+				return i;
 			found++;
 		}
 
-	return (BADIDX);
+	return BADIDX;
 }
 
 /* return list of found cores */
@@ -878,7 +878,7 @@
 
 	bcopy((uchar *) sii->coreid, (uchar *) coreid,
 	      (sii->numcores * sizeof(uint)));
-	return (sii->numcores);
+	return sii->numcores;
 }
 
 /* return current register mapping */
@@ -889,7 +889,7 @@
 	sii = SI_INFO(sih);
 	ASSERT(GOODREGS(sii->curmap));
 
-	return (sii->curmap);
+	return sii->curmap;
 }
 
 /*
@@ -903,7 +903,7 @@
 
 	idx = si_findcoreidx(sih, coreid, coreunit);
 	if (!GOODIDX(idx))
-		return (NULL);
+		return NULL;
 
 	if (CHIPTYPE(sih->socitype) == SOCI_AI)
 		return ai_setcoreidx(sih, idx);
@@ -1154,7 +1154,7 @@
 		ASSERT((n1 >= 2) && (n1 <= 7));
 		ASSERT((n2 >= 5) && (n2 <= 23));
 	} else if (pll_type == PLL_TYPE5) {
-		return (100000000);
+		return 100000000;
 	} else
 		ASSERT(0);
 	/* PLL types 3 and 7 use BASE2 (25Mhz) */
@@ -1183,17 +1183,17 @@
 
 		switch (mc) {
 		case CC_MC_BYPASS:
-			return (clock);
+			return clock;
 		case CC_MC_M1:
-			return (clock / m1);
+			return clock / m1;
 		case CC_MC_M1M2:
-			return (clock / (m1 * m2));
+			return clock / (m1 * m2);
 		case CC_MC_M1M2M3:
-			return (clock / (m1 * m2 * m3));
+			return clock / (m1 * m2 * m3);
 		case CC_MC_M1M3:
-			return (clock / (m1 * m3));
+			return clock / (m1 * m3);
 		default:
-			return (0);
+			return 0;
 		}
 	} else {
 		ASSERT(pll_type == PLL_TYPE2);
@@ -1212,7 +1212,7 @@
 		if ((mc & CC_T2MC_M3BYP) == 0)
 			clock /= m3;
 
-		return (clock);
+		return clock;
 	}
 }
 
@@ -1354,14 +1354,14 @@
 		if ((BUSTYPE(sii->pub.bustype) == PCI_BUS) &&
 		    (OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32))
 		     & PCI_CFG_GPIO_SCS))
-			return (SCC_SS_PCI);
+			return SCC_SS_PCI;
 		else
-			return (SCC_SS_XTAL);
+			return SCC_SS_XTAL;
 	} else if (sii->pub.ccrev < 10) {
 		cc = (chipcregs_t *) si_setcoreidx(&sii->pub, sii->curidx);
-		return (R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK);
+		return R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK;
 	} else			/* Insta-clock */
-		return (SCC_SS_XTAL);
+		return SCC_SS_XTAL;
 }
 
 /* return the ILP (slowclock) min or max frequency */
@@ -1378,32 +1378,32 @@
 	slowclk = si_slowclk_src(sii);
 	if (sii->pub.ccrev < 6) {
 		if (slowclk == SCC_SS_PCI)
-			return (max_freq ? (PCIMAXFREQ / 64)
-				: (PCIMINFREQ / 64));
+			return max_freq ? (PCIMAXFREQ / 64)
+				: (PCIMINFREQ / 64);
 		else
-			return (max_freq ? (XTALMAXFREQ / 32)
-				: (XTALMINFREQ / 32));
+			return max_freq ? (XTALMAXFREQ / 32)
+				: (XTALMINFREQ / 32);
 	} else if (sii->pub.ccrev < 10) {
 		div = 4 *
 		    (((R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >>
 		      SCC_CD_SHIFT) + 1);
 		if (slowclk == SCC_SS_LPO)
-			return (max_freq ? LPOMAXFREQ : LPOMINFREQ);
+			return max_freq ? LPOMAXFREQ : LPOMINFREQ;
 		else if (slowclk == SCC_SS_XTAL)
-			return (max_freq ? (XTALMAXFREQ / div)
-				: (XTALMINFREQ / div));
+			return max_freq ? (XTALMAXFREQ / div)
+				: (XTALMINFREQ / div);
 		else if (slowclk == SCC_SS_PCI)
-			return (max_freq ? (PCIMAXFREQ / div)
-				: (PCIMINFREQ / div));
+			return max_freq ? (PCIMAXFREQ / div)
+				: (PCIMINFREQ / div);
 		else
 			ASSERT(0);
 	} else {
 		/* Chipc rev 10 is InstaClock */
 		div = R_REG(sii->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;
 		div = 4 * (div + 1);
-		return (max_freq ? XTALMAXFREQ : (XTALMINFREQ / div));
+		return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
 	}
-	return (0);
+	return 0;
 }
 
 static void BCMINITFN(si_clkctl_setdelay) (si_info_t *sii, void *chipcregs)
@@ -1524,7 +1524,7 @@
 
 #ifdef BCMSDIO
 	case SDIO_BUS:
-		return (-1);
+		return -1;
 #endif				/* BCMSDIO */
 
 	case PCI_BUS:
@@ -1545,7 +1545,7 @@
 		 * by the value of XTAL_PU which *is* readable via gpioin.
 		 */
 		if (on && (in & PCI_CFG_GPIO_XTAL))
-			return (0);
+			return 0;
 
 		if (what & XTAL)
 			outen |= PCI_CFG_GPIO_XTAL;
@@ -1584,10 +1584,10 @@
 		}
 
 	default:
-		return (-1);
+		return -1;
 	}
 
-	return (0);
+	return 0;
 }
 
 /*
@@ -1609,7 +1609,7 @@
 		return FALSE;
 
 	if (PCI_FORCEHT(sii))
-		return (mode == CLK_FAST);
+		return mode == CLK_FAST;
 
 	return _si_clkctl_cc(sii, mode);
 }
@@ -1625,7 +1625,7 @@
 
 	/* chipcommon cores prior to rev6 don't support dynamic clock control */
 	if (sii->pub.ccrev < 6)
-		return (FALSE);
+		return FALSE;
 
 	/* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */
 	ASSERT(sii->pub.ccrev != 10);
@@ -1699,7 +1699,7 @@
 		si_setcoreidx(&sii->pub, origidx);
 		INTR_RESTORE(sii, intr_val);
 	}
-	return (mode == CLK_FAST);
+	return mode == CLK_FAST;
 }
 
 /* Build device path. Support SI, PCI, and JTAG for now. */
@@ -1752,26 +1752,26 @@
 
 	si_devpathvar(sih, varname, sizeof(varname), name);
 
-	return (getvar(NULL, varname));
+	return getvar(NULL, varname);
 }
 
 /* Get a variable, but only if it has a devpath prefix */
 int BCMATTACHFN(si_getdevpathintvar) (si_t *sih, const char *name)
 {
 #if defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS)
-	return (getintvar(NULL, name));
+	return getintvar(NULL, name);
 #else
 	char varname[SI_DEVPATH_BUFSZ + 32];
 
 	si_devpathvar(sih, varname, sizeof(varname), name);
 
-	return (getintvar(NULL, varname));
+	return getintvar(NULL, varname);
 #endif
 }
 
 char *si_getnvramflvar(si_t *sih, const char *name)
 {
-	return (getvar(NULL, name));
+	return getvar(NULL, name);
 }
 
 /* Concatenate the dev path with a varname into the given 'var' buffer
@@ -1923,7 +1923,7 @@
 
 	sii = SI_INFO(sih);
 
-	return (PCI(sii) && (sih->buscorerev <= 10));
+	return PCI(sii) && (sih->buscorerev <= 10);
 }
 
 /* Disable pcie_war_ovr for some platforms (sigh!)
@@ -2144,7 +2144,7 @@
 /* change logical "focus" to the gpio core for optimized access */
 void *si_gpiosetcore(si_t *sih)
 {
-	return (si_setcoreidx(sih, SI_CC_IDX));
+	return si_setcoreidx(sih, SI_CC_IDX);
 }
 
 /* mask&set gpiocontrol bits */
@@ -2165,7 +2165,7 @@
 	}
 
 	regoff = OFFSETOF(chipcregs_t, gpiocontrol);
-	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
+	return si_corereg(sih, SI_CC_IDX, regoff, mask, val);
 }
 
 /* mask&set gpio output enable bits */
@@ -2186,7 +2186,7 @@
 	}
 
 	regoff = OFFSETOF(chipcregs_t, gpioouten);
-	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
+	return si_corereg(sih, SI_CC_IDX, regoff, mask, val);
 }
 
 /* mask&set gpio output bits */
@@ -2207,7 +2207,7 @@
 	}
 
 	regoff = OFFSETOF(chipcregs_t, gpioout);
-	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
+	return si_corereg(sih, SI_CC_IDX, regoff, mask, val);
 }
 
 /* reserve one gpio */
@@ -2286,7 +2286,7 @@
 	regoff = 0;
 
 	regoff = OFFSETOF(chipcregs_t, gpioin);
-	return (si_corereg(sih, SI_CC_IDX, regoff, 0, 0));
+	return si_corereg(sih, SI_CC_IDX, regoff, 0, 0);
 }
 
 /* mask&set gpio interrupt polarity bits */
@@ -2306,7 +2306,7 @@
 	}
 
 	regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
-	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
+	return si_corereg(sih, SI_CC_IDX, regoff, mask, val);
 }
 
 /* mask&set gpio interrupt mask bits */
@@ -2326,7 +2326,7 @@
 	}
 
 	regoff = OFFSETOF(chipcregs_t, gpiointmask);
-	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
+	return si_corereg(sih, SI_CC_IDX, regoff, mask, val);
 }
 
 /* assign the gpio to an led */
@@ -2339,9 +2339,9 @@
 		return 0xffffffff;
 
 	/* gpio led powersave reg */
-	return (si_corereg
+	return si_corereg
 		(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask,
-		 val));
+		 val);
 }
 
 /* mask&set gpio timer val */
@@ -2354,9 +2354,9 @@
 	if (sih->ccrev < 16)
 		return 0xffffffff;
 
-	return (si_corereg(sih, SI_CC_IDX,
+	return si_corereg(sih, SI_CC_IDX,
 			   OFFSETOF(chipcregs_t, gpiotimerval), mask,
-			   gpiotimerval));
+			   gpiotimerval);
 }
 
 uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val)
@@ -2371,7 +2371,7 @@
 	offs =
 	    (updown ? OFFSETOF(chipcregs_t, gpiopulldown) :
 	     OFFSETOF(chipcregs_t, gpiopullup));
-	return (si_corereg(sih, SI_CC_IDX, offs, mask, val));
+	return si_corereg(sih, SI_CC_IDX, offs, mask, val);
 }
 
 uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val)
@@ -2392,7 +2392,7 @@
 	else
 		return 0xffffffff;
 
-	return (si_corereg(sih, SI_CC_IDX, offs, mask, val));
+	return si_corereg(sih, SI_CC_IDX, offs, mask, val);
 }
 
 void *BCMATTACHFN(si_gpio_handler_register) (si_t *sih, uint32 event,
@@ -2485,8 +2485,8 @@
 		return 0xffffffff;
 
 	offs = OFFSETOF(chipcregs_t, intmask);
-	return (si_corereg
-		(sih, SI_CC_IDX, offs, CI_GPIO, (enable ? CI_GPIO : 0)));
+	return si_corereg
+		(sih, SI_CC_IDX, offs, CI_GPIO, (enable ? CI_GPIO : 0));
 }
 
 /* Return the size of the specified SOCRAM bank */
@@ -2789,7 +2789,7 @@
 		cc = si_setcoreidx(sih, SI_CC_IDX);
 		sromctrl = R_REG(sii->osh, &cc->sromcontrol);
 		si_setcoreidx(sih, origidx);
-		return (sromctrl & SRC_PRESENT);
+		return sromctrl & SRC_PRESENT;
 	}
 
 	switch (CHIPID(sih->chip)) {
@@ -2820,9 +2820,9 @@
 		return (sih->chipst & CST4319_SPROM_OTP_SEL_MASK) ==
 		    CST4319_OTP_PWRDN;
 	case BCM4336_CHIP_ID:
-		return ((sih->chipst & CST4336_OTP_PRESENT) == 0);
+		return (sih->chipst & CST4336_OTP_PRESENT) == 0;
 	case BCM4330_CHIP_ID:
-		return ((sih->chipst & CST4330_OTP_PRESENT) == 0);
+		return (sih->chipst & CST4330_OTP_PRESENT) == 0;
 	case BCM4313_CHIP_ID:
 		return (sih->chipst & CST4313_OTP_PRESENT) == 0;
 		/* These chips always have their OTP on */