| commit | 910a17e57ab6cd22b300bde4ce5f633f175c7ccd | [log] [tgz] |
|---|---|---|
| author | Kirill A. Shutemov <kirill@shutemov.name> | Tue Sep 15 10:23:53 2009 +0100 |
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | Tue Sep 15 22:06:38 2009 +0100 |
| tree | 2a1dea95ca2d50192216500d90d9b0358af1dc1d | |
| parent | 59fcf48fdebe65e4774d2c7ec76b7845d281749a [diff] |
ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5. It's not true at least for CPUs based on Cortex-A8. List of CPUs with cache line size != 32 should be expanded later. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>