commit 919926aeb3e89825093c743dd54f04e42e7d9150
author Chris Wilson <chris@chris-wilson.co.uk> Fri Nov 12 13:42:53 2010 +0000
committer Chris Wilson <chris@chris-wilson.co.uk> Tue Nov 23 20:19:16 2010 +0000
tree d02a87578fd33a55035ef99f34af4ebce84394eb
parent 576ae4b8e46b4cb9d5390f4348c265329793d9bf

drm/i915: Thread the pipelining ring through the callers.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

drivers/gpu/drm/i915/i915_gem.c

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7d6ce34..465e07a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -42,11 +42,11 @@
 };
 
 static int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj,
-						  bool pipelined);
+						  struct intel_ring_buffer *pipelined);
 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
 static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
-					     int write);
+					     bool write);
 static int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
 						     uint64_t offset,
 						     uint64_t size);
@@ -1274,12 +1274,10 @@
 	mutex_lock(&dev->struct_mutex);
 	BUG_ON(obj->pin_count && !obj->pin_mappable);
 
-	if (obj->gtt_space) {
-		if (!obj->map_and_fenceable) {
-			ret = i915_gem_object_unbind(obj);
-			if (ret)
-				goto unlock;
-		}
+	if (!obj->map_and_fenceable) {
+		ret = i915_gem_object_unbind(obj);
+		if (ret)
+			goto unlock;
 	}
 
 	if (!obj->gtt_space) {
@@ -2637,7 +2635,7 @@
 	if (reg->gpu) {
 		int ret;
 
-		ret = i915_gem_object_flush_gpu_write_domain(obj, true);
+		ret = i915_gem_object_flush_gpu_write_domain(obj, NULL);
 		if (ret)
 			return ret;
 
@@ -2817,7 +2815,7 @@
 /** Flushes any GPU write domain for the object if it's dirty. */
 static int
 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj,
-				       bool pipelined)
+				       struct intel_ring_buffer *pipelined)
 {
 	struct drm_device *dev = obj->base.dev;
 
@@ -2828,7 +2826,7 @@
 	i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain);
 	BUG_ON(obj->base.write_domain);
 
-	if (pipelined)
+	if (pipelined && pipelined == obj->ring)
 		return 0;
 
 	return i915_gem_object_wait_rendering(obj, true);
@@ -2892,7 +2890,7 @@
 	if (obj->gtt_space == NULL)
 		return -EINVAL;
 
-	ret = i915_gem_object_flush_gpu_write_domain(obj, false);
+	ret = i915_gem_object_flush_gpu_write_domain(obj, NULL);
 	if (ret != 0)
 		return ret;
 
@@ -2931,7 +2929,7 @@
  */
 int
 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
-				     bool pipelined)
+				     struct intel_ring_buffer *pipelined)
 {
 	uint32_t old_read_domains;
 	int ret;
@@ -2940,7 +2938,7 @@
 	if (obj->gtt_space == NULL)
 		return -EINVAL;
 
-	ret = i915_gem_object_flush_gpu_write_domain(obj, true);
+	ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined);
 	if (ret)
 		return ret;
 
@@ -2984,7 +2982,7 @@
  * flushes to occur.
  */
 static int
-i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, int write)
+i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
 {
 	uint32_t old_write_domain, old_read_domains;
 	int ret;