| commit | 91f873453b70fe6cdb83409bee68e1023204c381 | [log] [tgz] |
|---|---|---|
| author | Lendacky, Thomas <Thomas.Lendacky@amd.com> | Wed Jul 02 13:04:34 2014 -0500 |
| committer | David S. Miller <davem@davemloft.net> | Mon Jul 07 21:38:06 2014 -0700 |
| tree | 044848d5cb059abc032487e472a953a2c8d5fbbf | |
| parent | f3f128d40c4cc263af8e30b009a3eb17655e912b [diff] |
amd-xgbe: Clear the proper MTL interrupt register When initializing the MTL interrupts the interrupt status register is written to instead of the interrupt enable register. Since no MTL interrupts are being enabled and the default state is for MTL interrupts to be disabled this did not cause a problem, but needs to be fixed to target the correct register. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>