tree ffcb529ae83a81e7840b9f57ccf11006fb15fd56
parent a91bb605ec5f93676e503267c89469d02c5b4cbc
author Rhyland Klein <rklein@nvidia.com> 1458590332 -0400
committer Thierry Reding <treding@nvidia.com> 1461840110 +0200

clk: tegra: Fix pllre Tegra210 and add pll_re_out1

Use a new Tegra210 version of the pll_register_pllre function to
allow setting the proper settings for the m and n div fields.

Additionally define PLL_RE_OUT1 on Tegra210.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[treding@nvidia.com: define PLLRE_OUT1 register offset]
Signed-off-by: Thierry Reding <treding@nvidia.com>