| commit | 92bd1bf089762dfee9fe34437068714a881c8bc0 | [log] [tgz] |
|---|---|---|
| author | Rodrigo Vivi <rodrigo.vivi@gmail.com> | Mon Mar 25 17:55:49 2013 -0300 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Tue Mar 26 09:04:01 2013 +0100 |
| tree | 2af7851320c1c2a2214fc1e4f0a97f677a951e53 | |
| parent | a42f704b71b252705f34fbe60ea6f4a76f891a78 [diff] |
drm/i915: HSW PM Frequency bits fix According to HSW PM programming guide, frequency bits starts at 24 instead of 25. v2: Paulo Zanoni noticed that only frequency bits can be set at GEN6_RPNSWREQ. All others are read only. CC: Ben Widawsky <ben@bwidawsk.net> CC: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>