tree 021c9a0fa6dfad8e3ca7855207bb0a1bc51f60f9
parent 26720ab97feac7153a7b5c3c79cf5d53a8531126
author Tim Gore <tim.gore@intel.com> 1458144826 +0000
committer Tvrtko Ursulin <tvrtko.ursulin@intel.com> 1458299549 +0000

drm/i915/gen9: add WaClearFlowControlGpgpuContextSave

This allows writes to EU flow control registers. Together
with SIP code from the user-mode driver this resolves a
hang seen in some pre-emption scenarios. Note that this
patch is just the kernel mode part of this workaround.

v2. Oops, add FLOW_CONTROL_ENABLE macro to i915_reg.h.

Signed-off-by: Tim Gore <tim.gore@intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1458144826-17269-1-git-send-email-tim.gore@intel.com