x86: Add cpu_mask_to_apicid_and
Impact: new API
Add a helper function that takes two cpumask's, and's them and then
returns the apicid of the result. This removes a need in io_apic.c
that uses a temporary cpumask to hold (mask & cfg->domain).
Signed-off-by: Mike Travis <travis@sgi.com>
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
diff --git a/arch/x86/include/asm/bigsmp/apic.h b/arch/x86/include/asm/bigsmp/apic.h
index dc6225c..99f9aba 100644
--- a/arch/x86/include/asm/bigsmp/apic.h
+++ b/arch/x86/include/asm/bigsmp/apic.h
@@ -129,6 +129,22 @@
return apicid;
}
+static inline unsigned int cpu_mask_to_apicid_and(const cpumask_t *cpumask,
+ const cpumask_t *andmask)
+{
+ int cpu;
+
+ /*
+ * We're using fixed IRQ delivery, can only return one phys APIC ID.
+ * May as well be the first.
+ */
+ while ((cpu = next_cpu(-1, *cpumask)) < nr_cpu_ids)
+ if (cpu_isset(cpu, *andmask))
+ return cpu_to_logical_apicid(cpu);
+
+ return BAD_APICID;
+}
+
static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
{
return cpuid_apic >> index_msb;
diff --git a/arch/x86/include/asm/es7000/apic.h b/arch/x86/include/asm/es7000/apic.h
index 4cac083..c2bed77 100644
--- a/arch/x86/include/asm/es7000/apic.h
+++ b/arch/x86/include/asm/es7000/apic.h
@@ -214,6 +214,53 @@
return apicid;
}
+static inline unsigned int cpu_mask_to_apicid_and(const cpumask_t *cpumask,
+ const cpumask_t *andmask)
+{
+ int num_bits_set;
+ int num_bits_set2;
+ int cpus_found = 0;
+ int cpu;
+ int apicid = 0;
+
+ num_bits_set = cpus_weight(*cpumask);
+ num_bits_set2 = cpus_weight(*andmask);
+ num_bits_set = min_t(int, num_bits_set, num_bits_set2);
+ /* Return id to all */
+ if (num_bits_set >= nr_cpu_ids)
+#if defined CONFIG_ES7000_CLUSTERED_APIC
+ return 0xFF;
+#else
+ return cpu_to_logical_apicid(0);
+#endif
+ /*
+ * The cpus in the mask must all be on the apic cluster. If are not
+ * on the same apicid cluster return default value of TARGET_CPUS.
+ */
+ while ((cpu = next_cpu(-1, *cpumask)) < nr_cpu_ids)
+ if (cpu_isset(cpu, *andmask)
+ apicid = cpu_to_logical_apicid(cpu);
+ while (cpus_found < num_bits_set) {
+ if (cpu_isset(cpu, *cpumask) && cpu_isset(cpu, *andmask)) {
+ int new_apicid = cpu_to_logical_apicid(cpu);
+ if (apicid_cluster(apicid) !=
+ apicid_cluster(new_apicid)) {
+ printk(KERN_WARNING
+ "%s: Not a valid mask!\n", __func__);
+#if defined CONFIG_ES7000_CLUSTERED_APIC
+ return 0xFF;
+#else
+ return cpu_to_logical_apicid(0);
+#endif
+ }
+ apicid = new_apicid;
+ cpus_found++;
+ }
+ cpu++;
+ }
+ return apicid;
+}
+
static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
{
return cpuid_apic >> index_msb;
diff --git a/arch/x86/include/asm/genapic_32.h b/arch/x86/include/asm/genapic_32.h
index b21ed21..325298a 100644
--- a/arch/x86/include/asm/genapic_32.h
+++ b/arch/x86/include/asm/genapic_32.h
@@ -58,6 +58,8 @@
unsigned (*get_apic_id)(unsigned long x);
unsigned long apic_id_mask;
unsigned int (*cpu_mask_to_apicid)(const cpumask_t *cpumask);
+ unsigned int (*cpu_mask_to_apicid_and)(const cpumask_t *cpumask,
+ const cpumask_t *andmask);
void (*vector_allocation_domain)(int cpu, cpumask_t *retmask);
#ifdef CONFIG_SMP
@@ -115,6 +117,7 @@
APICFUNC(get_apic_id) \
.apic_id_mask = APIC_ID_MASK, \
APICFUNC(cpu_mask_to_apicid) \
+ APICFUNC(cpu_mask_to_apicid_and) \
APICFUNC(vector_allocation_domain) \
APICFUNC(acpi_madt_oem_check) \
IPIFUNC(send_IPI_mask) \
diff --git a/arch/x86/include/asm/genapic_64.h b/arch/x86/include/asm/genapic_64.h
index a020e7d..301c7f4 100644
--- a/arch/x86/include/asm/genapic_64.h
+++ b/arch/x86/include/asm/genapic_64.h
@@ -31,6 +31,8 @@
void (*send_IPI_self)(int vector);
/* */
unsigned int (*cpu_mask_to_apicid)(const cpumask_t *cpumask);
+ unsigned int (*cpu_mask_to_apicid_and)(const cpumask_t *cpumask,
+ const cpumask_t *andmask);
unsigned int (*phys_pkg_id)(int index_msb);
unsigned int (*get_apic_id)(unsigned long x);
unsigned long (*set_apic_id)(unsigned int id);
diff --git a/arch/x86/include/asm/mach-default/mach_apic.h b/arch/x86/include/asm/mach-default/mach_apic.h
index c18896b..229b605 100644
--- a/arch/x86/include/asm/mach-default/mach_apic.h
+++ b/arch/x86/include/asm/mach-default/mach_apic.h
@@ -28,6 +28,7 @@
#define apic_id_registered (genapic->apic_id_registered)
#define init_apic_ldr (genapic->init_apic_ldr)
#define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
+#define cpu_mask_to_apicid_and (genapic->cpu_mask_to_apicid_and)
#define phys_pkg_id (genapic->phys_pkg_id)
#define vector_allocation_domain (genapic->vector_allocation_domain)
#define read_apic_id() (GET_APIC_ID(apic_read(APIC_ID)))
@@ -66,6 +67,15 @@
return cpus_addr(*cpumask)[0];
}
+static inline unsigned int cpu_mask_to_apicid(const cpumask_t *cpumask,
+ const cpumask_t *andmask)
+{
+ unsigned long mask1 = cpus_addr(*cpumask)[0];
+ unsigned long mask2 = cpus_addr(*andmask)[0];
+
+ return (unsigned int)(mask1 & mask2);
+}
+
static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
{
return cpuid_apic >> index_msb;
diff --git a/arch/x86/include/asm/mach-generic/mach_apic.h b/arch/x86/include/asm/mach-generic/mach_apic.h
index e430f47..48553e9 100644
--- a/arch/x86/include/asm/mach-generic/mach_apic.h
+++ b/arch/x86/include/asm/mach-generic/mach_apic.h
@@ -24,6 +24,7 @@
#define check_phys_apicid_present (genapic->check_phys_apicid_present)
#define check_apicid_used (genapic->check_apicid_used)
#define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
+#define cpu_mask_to_apicid_and (genapic->cpu_mask_to_apicid_and)
#define vector_allocation_domain (genapic->vector_allocation_domain)
#define enable_apic_mode (genapic->enable_apic_mode)
#define phys_pkg_id (genapic->phys_pkg_id)
diff --git a/arch/x86/include/asm/numaq/apic.h b/arch/x86/include/asm/numaq/apic.h
index 1df7ebe..abf668c 100644
--- a/arch/x86/include/asm/numaq/apic.h
+++ b/arch/x86/include/asm/numaq/apic.h
@@ -127,6 +127,12 @@
return (int) 0xF;
}
+static inline unsigned int cpu_mask_to_apicid_and(const cpumask_t *cpumask,
+ const cpumask_t *andmask)
+{
+ return (int) 0xF;
+}
+
/* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
{
diff --git a/arch/x86/include/asm/summit/apic.h b/arch/x86/include/asm/summit/apic.h
index 437dc83..cbcc2c7 100644
--- a/arch/x86/include/asm/summit/apic.h
+++ b/arch/x86/include/asm/summit/apic.h
@@ -170,6 +170,45 @@
return apicid;
}
+static inline unsigned int cpu_mask_to_apicid_and(const cpumask_t *cpumask,
+ const cpumask_t *andmask)
+{
+ int num_bits_set;
+ int num_bits_set2;
+ int cpus_found = 0;
+ int cpu;
+ int apicid = 0;
+
+ num_bits_set = cpus_weight(*cpumask);
+ num_bits_set2 = cpus_weight(*andmask);
+ num_bits_set = min_t(int, num_bits_set, num_bits_set2);
+ /* Return id to all */
+ if (num_bits_set >= nr_cpu_ids)
+ return 0xFF;
+ /*
+ * The cpus in the mask must all be on the apic cluster. If are not
+ * on the same apicid cluster return default value of TARGET_CPUS.
+ */
+ while ((cpu = next_cpu(-1, *cpumask)) < nr_cpu_ids)
+ if (cpu_isset(cpu, *andmask)
+ apicid = cpu_to_logical_apicid(cpu);
+ while (cpus_found < num_bits_set) {
+ if (cpu_isset(cpu, *cpumask) && cpu_isset(cpu, *andmask)) {
+ int new_apicid = cpu_to_logical_apicid(cpu);
+ if (apicid_cluster(apicid) !=
+ apicid_cluster(new_apicid)) {
+ printk(KERN_WARNING
+ "%s: Not a valid mask!\n", __func__);
+ return 0xFF;
+ }
+ apicid = apicid | new_apicid;
+ cpus_found++;
+ }
+ cpu++;
+ }
+ return apicid;
+}
+
/* cpuid returns the value latched in the HW at reset, not the APIC ID
* register's value. For any box whose BIOS changes APIC IDs, like
* clustered APIC systems, we must use hard_smp_processor_id.