drm/nouveau: move set_tile_region to nouveau_exec_engine
In the very least VPE (PMPEG and friends) also has this style of tile
region regs, lets make them just work if/when they get added.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index fb33d4f..413e2ba 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -302,6 +302,7 @@
void (*context_del)(struct nouveau_channel *, int engine);
int (*object_new)(struct nouveau_channel *, int engine,
u32 handle, u16 class);
+ void (*set_tile_region)(struct drm_device *dev, int i);
void (*tlb_flush)(struct drm_device *, int engine);
};
@@ -393,7 +394,6 @@
int (*object_new)(struct nouveau_channel *chan, u32 handle, u16 class);
void (*tlb_flush)(struct drm_device *dev);
- void (*set_tile_region)(struct drm_device *dev, int i);
};
struct nouveau_display_engine {
@@ -1151,18 +1151,15 @@
/* nv10_graph.c */
extern int nv10_graph_create(struct drm_device *);
extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
-extern void nv10_graph_set_tile_region(struct drm_device *dev, int i);
extern struct nouveau_bitfield nv10_graph_intr[];
extern struct nouveau_bitfield nv10_graph_nstatus[];
/* nv20_graph.c */
extern int nv20_graph_create(struct drm_device *);
-extern void nv20_graph_set_tile_region(struct drm_device *dev, int i);
/* nv40_graph.c */
extern int nv40_graph_create(struct drm_device *);
extern void nv40_grctx_init(struct nouveau_grctx *);
-extern void nv40_graph_set_tile_region(struct drm_device *dev, int i);
/* nv50_graph.c */
extern int nv50_graph_create(struct drm_device *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index cf1731b..9c7bc3f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -51,8 +51,7 @@
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
- int i = tile - dev_priv->tile.reg;
+ int i = tile - dev_priv->tile.reg, j;
unsigned long save;
nouveau_fence_unref(&tile->fence);
@@ -70,7 +69,10 @@
nouveau_wait_for_idle(dev);
pfb->set_tile_region(dev, i);
- pgraph->set_tile_region(dev, i);
+ for (j = 0; j < NVOBJ_ENGINE_NR; j++) {
+ if (dev_priv->eng[j] && dev_priv->eng[j]->set_tile_region)
+ dev_priv->eng[j]->set_tile_region(dev, i);
+ }
pfifo->cache_pull(dev, true);
pfifo->reassign(dev, true);
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 2a127ed..052a267 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -121,7 +121,6 @@
engine->graph.takedown = nouveau_stub_takedown;
engine->graph.channel = nvc0_graph_channel;
engine->graph.fifo_access = nvc0_graph_fifo_access;
- engine->graph.set_tile_region = nv10_graph_set_tile_region;
engine->fifo.channels = 32;
engine->fifo.init = nv10_fifo_init;
engine->fifo.takedown = nv04_fifo_fini;
@@ -174,7 +173,6 @@
engine->graph.takedown = nouveau_stub_takedown;
engine->graph.channel = nvc0_graph_channel;
engine->graph.fifo_access = nvc0_graph_fifo_access;
- engine->graph.set_tile_region = nv20_graph_set_tile_region;
engine->fifo.channels = 32;
engine->fifo.init = nv10_fifo_init;
engine->fifo.takedown = nv04_fifo_fini;
@@ -227,7 +225,6 @@
engine->graph.takedown = nouveau_stub_takedown;
engine->graph.channel = nvc0_graph_channel;
engine->graph.fifo_access = nvc0_graph_fifo_access;
- engine->graph.set_tile_region = nv20_graph_set_tile_region;
engine->fifo.channels = 32;
engine->fifo.init = nv10_fifo_init;
engine->fifo.takedown = nv04_fifo_fini;
@@ -283,7 +280,6 @@
engine->graph.takedown = nouveau_stub_takedown;
engine->graph.fifo_access = nvc0_graph_fifo_access;
engine->graph.channel = nvc0_graph_channel;
- engine->graph.set_tile_region = nv40_graph_set_tile_region;
engine->fifo.channels = 32;
engine->fifo.init = nv40_fifo_init;
engine->fifo.takedown = nv04_fifo_fini;
diff --git a/drivers/gpu/drm/nouveau/nv10_graph.c b/drivers/gpu/drm/nouveau/nv10_graph.c
index afc456b..0930c6c 100644
--- a/drivers/gpu/drm/nouveau/nv10_graph.c
+++ b/drivers/gpu/drm/nouveau/nv10_graph.c
@@ -893,7 +893,7 @@
kfree(pgraph_ctx);
}
-void
+static void
nv10_graph_set_tile_region(struct drm_device *dev, int i)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -1143,6 +1143,7 @@
pgraph->base.context_new = nv10_graph_context_new;
pgraph->base.context_del = nv10_graph_context_del;
pgraph->base.object_new = nv04_graph_object_new;
+ pgraph->base.set_tile_region = nv10_graph_set_tile_region;
NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
nouveau_irq_register(dev, 12, nv10_graph_isr);
diff --git a/drivers/gpu/drm/nouveau/nv20_graph.c b/drivers/gpu/drm/nouveau/nv20_graph.c
index ce83f02..b47e9e2 100644
--- a/drivers/gpu/drm/nouveau/nv20_graph.c
+++ b/drivers/gpu/drm/nouveau/nv20_graph.c
@@ -470,7 +470,7 @@
chan->engctx[engine] = NULL;
}
-void
+static void
nv20_graph_set_tile_region(struct drm_device *dev, int i)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -730,6 +730,7 @@
pgraph->base.context_new = nv20_graph_context_new;
pgraph->base.context_del = nv20_graph_context_del;
pgraph->base.object_new = nv04_graph_object_new;
+ pgraph->base.set_tile_region = nv20_graph_set_tile_region;
pgraph->grctx_user = 0x0028;
if (dev_priv->card_type == NV_20) {
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index f0c6a64..638c887 100644
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -207,7 +207,7 @@
return ret;
}
-void
+static void
nv40_graph_set_tile_region(struct drm_device *dev, int i)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -525,6 +525,7 @@
pgraph->base.context_new = nv40_graph_context_new;
pgraph->base.context_del = nv40_graph_context_del;
pgraph->base.object_new = nv40_graph_object_new;
+ pgraph->base.set_tile_region = nv40_graph_set_tile_region;
NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
nouveau_irq_register(dev, 12, nv40_graph_isr);