tree 9daf7340c40c56aceefb777588c1c2bfc0ba2f02
parent 1faf8692bdc2da1e12c7f2ecda3a9e629ac9b05b
author Geert Uytterhoeven <geert+renesas@glider.be> 1462192592 +0200
committer Geert Uytterhoeven <geert+renesas@glider.be> 1465207107 +0200

clk: renesas: Add r8a7796 CPG Core Clock Definitions

Add all R-Car M3-W Clock Pulse Generator Core Clock Outputs, as listed
in Table 8.2b ("List of Clocks [R-Car M3-W]") of the R-Car Gen3
datasheet (rev. 0.51 + Errata for Rev051 Mar 31 2016).

Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, and SSPSRC) are
not included, as they are used as internal clock sources only, and never
referenced from DT.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>