drm/msm/dsi-staging: add support for dsi dynamic clock switch
This change adds support for dynamic switching of dsi clocks
to avoid RF interference issues. Also with dynamic dsi clock
switch feature coming into picture, now populate the supported
refresh rate as list instead of providing a range. Modify the
logic to enumerate all the modes in dsi driver, taking dynamic
bit clocks, resolutions and refresh rates into account.
Change-Id: I5b6e62bc935cf2234bdd96fcb3c7537b4e735fff
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
index 3d6711f..ebc699a 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
@@ -107,6 +107,9 @@
phy->hw.base = ptr;
+ ptr = msm_ioremap(pdev, "dyn_refresh_base", phy->name);
+ phy->hw.dyn_pll_base = ptr;
+
pr_debug("[%s] map dsi_phy registers to %pK\n",
phy->name, phy->hw.base);
@@ -616,11 +619,8 @@
return -EINVAL;
}
- mutex_lock(&dsi_phy->phy_lock);
-
pr_debug("[PHY_%d] Skipping validation\n", dsi_phy->index);
- mutex_unlock(&dsi_phy->phy_lock);
return rc;
}
@@ -848,7 +848,7 @@
rc = phy->hw.ops.calculate_timing_params(&phy->hw,
&phy->mode,
&config->common_config,
- &phy->cfg.timing);
+ &phy->cfg.timing, false);
if (rc) {
pr_err("[%s] failed to set timing, rc=%d\n", phy->name, rc);
goto error;
@@ -866,6 +866,27 @@
return rc;
}
+/* update dsi phy timings for dynamic clk switch use case */
+int dsi_phy_update_phy_timings(struct msm_dsi_phy *phy,
+ struct dsi_host_config *config)
+{
+ int rc = 0;
+
+ if (!phy || !config) {
+ pr_err("invalid argument\n");
+ return -EINVAL;
+ }
+
+ memcpy(&phy->mode, &config->video_timing, sizeof(phy->mode));
+ rc = phy->hw.ops.calculate_timing_params(&phy->hw, &phy->mode,
+ &config->common_config,
+ &phy->cfg.timing, true);
+ if (rc)
+ pr_err("failed to calculate phy timings %d\n", rc);
+
+ return rc;
+}
+
int dsi_phy_lane_reset(struct msm_dsi_phy *phy)
{
int ret = 0;
@@ -1030,10 +1051,111 @@
rc = phy->hw.ops.phy_timing_val(&phy->cfg.timing, timing, size);
if (!rc)
phy->cfg.is_phy_timing_present = true;
+
mutex_unlock(&phy->phy_lock);
return rc;
}
+/**
+ * dsi_phy_dynamic_refresh_trigger() - trigger dynamic refresh
+ * @phy: DSI PHY handle
+ * @is_master: Boolean to indicate if for master or slave.
+ */
+void dsi_phy_dynamic_refresh_trigger(struct msm_dsi_phy *phy, bool is_master)
+{
+ u32 off;
+
+ if (!phy)
+ return;
+
+ mutex_lock(&phy->phy_lock);
+ /*
+ * program PLL_SWI_INTF_SEL and SW_TRIGGER bit only for
+ * master and program SYNC_MODE bit only for slave.
+ */
+ if (is_master)
+ off = BIT(DYN_REFRESH_INTF_SEL) | BIT(DYN_REFRESH_SWI_CTRL) |
+ BIT(DYN_REFRESH_SW_TRIGGER);
+ else
+ off = BIT(DYN_REFRESH_SYNC_MODE) | BIT(DYN_REFRESH_SWI_CTRL);
+
+ if (phy->hw.ops.dyn_refresh_ops.dyn_refresh_helper)
+ phy->hw.ops.dyn_refresh_ops.dyn_refresh_helper(&phy->hw, off);
+
+ mutex_unlock(&phy->phy_lock);
+}
+
+/**
+ * dsi_phy_config_dynamic_refresh() - Configure dynamic refresh registers
+ * @phy: DSI PHY handle
+ * @delay: pipe delays for dynamic refresh
+ * @is_master: Boolean to indicate if for master or slave.
+ */
+void dsi_phy_config_dynamic_refresh(struct msm_dsi_phy *phy,
+ struct dsi_dyn_clk_delay *delay,
+ bool is_master)
+{
+ struct dsi_phy_cfg *cfg;
+
+ if (!phy)
+ return;
+
+ mutex_lock(&phy->phy_lock);
+
+ cfg = &phy->cfg;
+
+ if (phy->hw.ops.dyn_refresh_ops.dyn_refresh_config)
+ phy->hw.ops.dyn_refresh_ops.dyn_refresh_config(&phy->hw, cfg,
+ is_master);
+ if (phy->hw.ops.dyn_refresh_ops.dyn_refresh_pipe_delay)
+ phy->hw.ops.dyn_refresh_ops.dyn_refresh_pipe_delay(
+ &phy->hw, delay);
+
+ mutex_unlock(&phy->phy_lock);
+}
+
+/**
+ * dsi_phy_cache_phy_timings - cache the phy timings calculated as part of
+ * dynamic refresh.
+ * @phy: DSI PHY Handle.
+ * @dst: Pointer to cache location.
+ * @size: Number of phy lane settings.
+ */
+int dsi_phy_dyn_refresh_cache_phy_timings(struct msm_dsi_phy *phy, u32 *dst,
+ u32 size)
+{
+ int rc = 0;
+
+ if (!phy || !dst || !size)
+ return -EINVAL;
+
+ if (phy->hw.ops.dyn_refresh_ops.cache_phy_timings)
+ rc = phy->hw.ops.dyn_refresh_ops.cache_phy_timings(
+ &phy->cfg.timing, dst, size);
+
+ if (rc)
+ pr_err("failed to cache phy timings %d\n", rc);
+
+ return rc;
+}
+
+/**
+ * dsi_phy_dynamic_refresh_clear() - clear dynamic refresh config
+ * @phy: DSI PHY handle
+ */
+void dsi_phy_dynamic_refresh_clear(struct msm_dsi_phy *phy)
+{
+ if (!phy)
+ return;
+
+ mutex_lock(&phy->phy_lock);
+
+ if (phy->hw.ops.dyn_refresh_ops.dyn_refresh_helper)
+ phy->hw.ops.dyn_refresh_ops.dyn_refresh_helper(&phy->hw, 0);
+
+ mutex_unlock(&phy->phy_lock);
+}
+
void dsi_phy_drv_register(void)
{
platform_driver_register(&dsi_phy_platform_driver);