mmc: sdhci-msm: add offset to CMDQ_COMMAND_DEBUG_RAM_x registers access
Starting from MCI_VERSION 4.2.0 use a different offset for the following
registers:
PERIPH_SS_SDC1_SDCC_HC_CMDQ_COMMAND_DEBUG_RAM_n
PERIPH_SS_SDC1_SDCC_HC_CMDQ_COMMAND_DEBUG_RAM_WRAPAROUND
PERIPH_SS_SDC1_SDCC_HC_CMDQ_COMMAND_DEBUG_RAM_OVERLAP
In addition, move dump debug ram functionality to the MSM specific file.
Change-Id: I3b0f5101150de9f2c190ce69b306bd151cbb65ae
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
[xiaonian@codeaurora.org: fixed trivial merge conflict]
Signed-off-by: Xiaonian Wang <xiaonian@codeaurora.org>
diff --git a/drivers/mmc/host/cmdq_hci.c b/drivers/mmc/host/cmdq_hci.c
index 0eb1ba0..c4744d2 100644
--- a/drivers/mmc/host/cmdq_hci.c
+++ b/drivers/mmc/host/cmdq_hci.c
@@ -131,23 +131,6 @@
#define DRV_NAME "cmdq-host"
-static void cmdq_dump_debug_ram(struct cmdq_host *cq_host)
-{
- int i = 0;
-
- pr_err("---- Debug RAM dump ----\n");
- pr_err(DRV_NAME ": Debug RAM wrap-around: 0x%08x | Debug RAM overlap: 0x%08x\n",
- cmdq_readl(cq_host, CQ_CMD_DBG_RAM_WA),
- cmdq_readl(cq_host, CQ_CMD_DBG_RAM_OL));
-
- while (i < 16) {
- pr_err(DRV_NAME ": Debug RAM dump [%d]: 0x%08x\n", i,
- cmdq_readl(cq_host, CQ_CMD_DBG_RAM + (0x4 * i)));
- i++;
- }
- pr_err("-------------------------\n");
-}
-
static void cmdq_dumpregs(struct cmdq_host *cq_host)
{
struct mmc_host *mmc = cq_host->mmc;
@@ -192,7 +175,6 @@
cmdq_readl(cq_host, CQ_VENDOR_CFG));
pr_err(DRV_NAME ": ===========================================\n");
- cmdq_dump_debug_ram(cq_host);
if (cq_host->ops->dump_vendor_regs)
cq_host->ops->dump_vendor_regs(mmc);
}
diff --git a/drivers/mmc/host/cmdq_hci.h b/drivers/mmc/host/cmdq_hci.h
index fd52d1c..2c917069 100644
--- a/drivers/mmc/host/cmdq_hci.h
+++ b/drivers/mmc/host/cmdq_hci.h
@@ -114,11 +114,6 @@
#define CQIC_DEFAULT_ICCTH 31
#define CQIC_DEFAULT_ICTOVAL 1
-#define CQ_CMD_DBG_RAM 0x158
-#define CQ_CMD_DBG_RAM_WA 0x198
-#define CQ_CMD_DBG_RAM_OL 0x19C
-
-
/* attribute fields */
#define VALID(x) ((x & 1) << 0)
#define END(x) ((x & 1) << 1)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 47010c2..7c3e280 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -57,6 +57,7 @@
#define CORE_VERSION_MAJOR_MASK 0xF0000000
#define CORE_VERSION_MAJOR_SHIFT 28
#define CORE_VERSION_TARGET_MASK 0x000000FF
+#define SDHCI_MSM_VER_420 0x49
#define CORE_GENERICS 0x70
#define SWITCHABLE_SIGNALLING_VOL (1 << 29)
@@ -154,6 +155,10 @@
#define CORE_CDC_ERROR_CODE_MASK 0x7000000
+#define CQ_CMD_DBG_RAM 0x110
+#define CQ_CMD_DBG_RAM_WA 0x150
+#define CQ_CMD_DBG_RAM_OL 0x154
+
#define CORE_CSR_CDC_GEN_CFG 0x178
#define CORE_CDC_SWITCH_BYPASS_OFF (1 << 0)
#define CORE_CDC_SWITCH_RC_EN (1 << 1)
@@ -2910,6 +2915,28 @@
}
#define MAX_TEST_BUS 60
+#define DRV_NAME "cmdq-host"
+static void sdhci_msm_cmdq_dump_debug_ram(struct sdhci_msm_host *msm_host)
+{
+ int i = 0;
+ struct cmdq_host *cq_host = mmc_cmdq_private(msm_host->mmc);
+ u32 version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
+ u16 minor = version & CORE_VERSION_TARGET_MASK;
+ /* registers offset changed starting from 4.2.0 */
+ int offset = minor >= SDHCI_MSM_VER_420 ? 0 : 0x48;
+
+ pr_err("---- Debug RAM dump ----\n");
+ pr_err(DRV_NAME ": Debug RAM wrap-around: 0x%08x | Debug RAM overlap: 0x%08x\n",
+ cmdq_readl(cq_host, CQ_CMD_DBG_RAM_WA + offset),
+ cmdq_readl(cq_host, CQ_CMD_DBG_RAM_OL + offset));
+
+ while (i < 16) {
+ pr_err(DRV_NAME ": Debug RAM dump [%d]: 0x%08x\n", i,
+ cmdq_readl(cq_host, CQ_CMD_DBG_RAM + offset + (4 * i)));
+ i++;
+ }
+ pr_err("-------------------------\n");
+}
void sdhci_msm_dump_vendor_regs(struct sdhci_host *host)
{
@@ -2921,6 +2948,8 @@
u32 debug_reg[MAX_TEST_BUS] = {0};
pr_info("----------- VENDOR REGISTER DUMP -----------\n");
+ sdhci_msm_cmdq_dump_debug_ram(msm_host);
+
pr_info("Data cnt: 0x%08x | Fifo cnt: 0x%08x | Int sts: 0x%08x\n",
readl_relaxed(msm_host->core_mem + CORE_MCI_DATA_CNT),
readl_relaxed(msm_host->core_mem + CORE_MCI_FIFO_CNT),