tree 3d22d9bf1dd46cb5ac2890c6887936d8ea6b6131
parent 037d768fed48a450c2533affa8a3817cf2d7d9c9
author Sandeep Panda <spanda@codeaurora.org> 1505911086 +0530
committer Sandeep Panda <spanda@codeaurora.org> 1505927583 +0530

clk: qcom: ensure dsiclk_sel bit is programmed before PLL start

In the current implementation, DSI PLL driver is overriding
set_parent API of mux clock to program the current parent index
in HW. But for use cases where parent of pixel mux clock is not
changing but rate is changing, then dsiclk_sel bit is not getting
programed because clock framework won't call set_parent API since
the parent has not changed. So cache the current parent index and
always ensure it is programed before PLL start happens.

Change-Id: Ia9a24165a49950620199d1afc6c9e5f01d3214e8
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>