| commit | 9abafa021e223f04d6589ee2b977bbaf2e1f1367 | [log] [tgz] |
|---|---|---|
| author | Stephen Warren <swarren@nvidia.com> | Thu Apr 12 14:13:05 2012 -0600 |
| committer | Stephen Warren <swarren@nvidia.com> | Wed Apr 25 15:22:09 2012 -0600 |
| tree | 6029d68e9dc837b40677282e459fc807aa76e581 | |
| parent | 7ff4db0967bd7d617c77dc5a66c0d95166277817 [diff] |
ARM: tegra: change pll_p_out4's rate to 24MHz pll_p_out4 is used on all/most Tegra boards to drive the cdev2 output pin to provide a reference clock to a ULPI USB PHY. This reference clock must run at 24MHz, and the cdev2 output has no additional dividers. Remove board-paz00.c's now-duplicate initialization of this clock. Reported-by: Marc Dietrich <marvin24@gmx.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>