| commit | 9bd9ddb7f89edae241d2da78e3119f226b9b0cf6 | [log] [tgz] |
|---|---|---|
| author | Jisheng Zhang <jszhang@marvell.com> | Wed Mar 30 19:55:21 2016 +0800 |
| committer | David S. Miller <davem@davemloft.net> | Thu Mar 31 15:15:01 2016 -0400 |
| tree | d276b0b55aaeb9ca6efbefc74c79e0f3fb4f5882 | |
| parent | b7854efce20be7c7bcd43424dee027124e9af27f [diff] |
net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES The mvneta is also used in some Marvell berlin family SoCs which may have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE usage with L1_CACHE_BYTES. And since dma_alloc_coherent() is always cacheline size aligned, so remove the align checks. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>