| commit | 9c6344b3fa547ce7ec78da95134d92d9f9309b31 | [log] [tgz] |
|---|---|---|
| author | Nicolin Chen <Guangyu.Chen@freescale.com> | Wed Apr 30 18:54:05 2014 +0800 |
| committer | Mark Brown <broonie@linaro.org> | Mon May 05 12:26:05 2014 -0700 |
| tree | 4fc10c4e0474c45a7facd093949e3c822bff94b7 | |
| parent | 0b8643900a1bff32ad8bf17ef1f5d57b6d490502 [diff] |
ASoC: fsl_spdif: Use clk_set_rate() for spdif root clock only The clock mux for the Freescale S/PDIF controller has eight clock sources while most of them are from other moudles and even system clocks that do not allow a rate-changing operation. So we here only allow the clk_set_rate() and clk_round_rate() happened to spdif root clock, the private clock for S/PDIF controller. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>