drm/i915: Basic shared dpll support for WRPLLs
Just filing in names and ids, but not yet officially registering them
so that the hw state cross checker doesn't completely freak out about
them. Still since we do already read out and cross check
config->shared_dpll the basics are now there to flesh out the wrpll
shared dpll implementation.
The idea is now to roll out all the callbacks step-by-step and then at
the end switch to the shared dpll framework. This way hw and sw
changes are clearly separated.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
[imre: added const to hsw_ddi_pll_names (Damien)]
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 195d52e..bf6f1c2 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -784,9 +784,11 @@
if (reg == WRPLL_CTL1) {
plls->wrpll1_refcount++;
intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
+ intel_crtc->config.shared_dpll = DPLL_ID_WRPLL1;
} else {
plls->wrpll2_refcount++;
intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
+ intel_crtc->config.shared_dpll = DPLL_ID_WRPLL2;
}
}
@@ -1315,10 +1317,25 @@
}
}
+static char *hsw_ddi_pll_names[] = {
+ "WRPLL 1",
+ "WRPLL 2",
+};
+
void intel_ddi_pll_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t val = I915_READ(LCPLL_CTL);
+ int i;
+
+ /* Dummy setup until everything is moved over to avoid upsetting the hw
+ * state cross checker. */
+ dev_priv->num_shared_dpll = 0;
+
+ for (i = 0; i < 2; i++) {
+ dev_priv->shared_dplls[i].id = i;
+ dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
+ }
/* The LCPLL register should be turned on by the BIOS. For now let's
* just check its state and print errors in case something is wrong.