drm/nv50-/disp: dump channel state when update method fails
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index e94866e..9a0cab9 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -1058,6 +1058,7 @@
static void
nv50_disp_intr_error(struct nv50_disp_priv *priv, int chid)
{
+ struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass;
u32 data = nv_rd32(priv, 0x610084 + (chid * 0x08));
u32 addr = nv_rd32(priv, 0x610080 + (chid * 0x08));
u32 code = (addr & 0x00ff0000) >> 16;
@@ -1078,6 +1079,37 @@
et ? et->name : etunk, ec ? ec->name : ecunk,
chid, mthd, data);
+ if (chid == 0) {
+ switch (mthd) {
+ case 0x0080:
+ nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 0,
+ impl->mthd.core);
+ break;
+ default:
+ break;
+ }
+ } else
+ if (chid <= 2) {
+ switch (mthd) {
+ case 0x0080:
+ nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 1,
+ impl->mthd.base);
+ break;
+ default:
+ break;
+ }
+ } else
+ if (chid <= 4) {
+ switch (mthd) {
+ case 0x0080:
+ nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 3,
+ impl->mthd.ovly);
+ break;
+ default:
+ break;
+ }
+ }
+
nv_wr32(priv, 0x610020, 0x00010000 << chid);
nv_wr32(priv, 0x610080 + (chid * 0x08), 0x90000000);
}